Glen R Haas

US Patent:

20020002573, Jan 3, 2002

Filed:

Mar 1, 2001

Appl. No.:

09/796415

Inventors:

George Landers - Mt. View CA, US
Earle Jennings - San Jose CA, US
Tim Smith - Dallas TX, US
Glen Haas - Plano TX, US

Assignee:

Infinite Technology Corporation.

International Classification:

G06F007/38

US Classification:

708/501000, 708/503000

Abstract:

A reconfigurable processor includes at least three (3) MacroSequencers ()-() which are configured in an array. Each of the MacroSequencers is operable to receive on a separate one of four buses () an input from the other three MacroSequencers and from itself in a feedback manner. In addition, a control bus () is operable to provide control signals to all of the MacroSequencers for the purpose of controlling the instruction sequence associated therewith and also for inputting instructions thereto. Each of the MacroSequencers includes a plurality of executable units having inputs and outputs and each for providing an associated execution algorithm. The outputs of the execution units are input to an output selector which selects the outputs for outputs on at least one external output and on at least one feedback path. An input selector () is provided having an input for receiving at least one external output and at least the feedback path. These are selected between for input to select ones of the execution units. An instruction memory () contains an instruction word that is operable to control configurations of the datapath through the execution units for a given instruction cycle. This instruction word can be retrieved from the instruction memory (), the stored instructions therein sequenced through to change the configuration of the datapath for subsequent instruction cycles.

US Patent:

53921852, Feb 21, 1995

Filed:

May 29, 1992

Appl. No.:

7/890899

Inventors:

Glen R. Haas - Plano TX
Thomas E. Nagle - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H02H 904

US Classification:

361 56

Abstract:

In one form of the invention, an Electrostatic Discharge protection device containing at least one heterojunction transistor is disclosed. In another embodiment, an Electrostatic Discharge protection circuit comprises: a first terminal contact 20; an NPN heterojunction bipolar transistor Q2; a PNP bipolar transistor Q1; a base-emitter shunt resistor R2; an emitter of said PNP transistor connected to said first terminal contact; a base of said PNP transistor connected to collector of said NPN transistor; a collector of said PNP transistor connected to a base of said NPN transistor; and an emitter of said NPN transistor connected to a second terminal contact 22, with said base-emitter shunt resistor connected between said base of said NPN transistor and an emitter of said NPN transistor, whereby a low-capacitance device capable of protecting semiconductor devices from electrostatic discharges in excess of 4000 Volts results. Other devices, systems, and methods are also disclosed.

US Patent:

53769090, Dec 27, 1994

Filed:

May 21, 1993

Appl. No.:

8/065691

Inventors:

Stephen R. Nelson - Richardson TX
Buford H. Carter - Richardson TX
Tammy J. Lahutsky - Plano TX
Glen R. Haas - Plano TX
Dennis D. Davis - Garland TX
Charles W. Suckling - Rushden, GB2
Glenn Collinson - Hitchin, GB2

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2328

US Classification:

333247

Abstract:

This is a package [10] for an rf device [11] operable with a characteristic impedance providing a plurality of terminals [12-19] and [101] for effecting circuit connections to the device, the connection between at least one of the terminals and the device being matched in relation to the characteristic impedance. Other devices and methods are also disclosed.

US Patent:

56635974, Sep 2, 1997

Filed:

Nov 23, 1994

Appl. No.:

8/344798

Inventors:

Stephen R. Nelson - Richardson TX
Buford H. Carter - Richardson TX
Dennis D. Davis - Garland TX
Tammy J. Lahutsky - Plano TX
John Barnett - Mesquite TX
Glen R. Haas - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23495
H01L 2348
H01L 2352

US Classification:

257734

Abstract:

This is a device package comprising: a leadframe comprising a plurality of leads for effecting circuit connections to the device; and a metal ground piece connected to the leadframe. Other devices and methods are also disclosed.

US Patent:

55372848, Jul 16, 1996

Filed:

Dec 23, 1994

Appl. No.:

8/363140

Inventors:

Glen R. Haas - Plano TX
Thomas E. Nagle - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H02H 904

US Classification:

361 56

Abstract:

In one form of the invention, an Electrostatic Discharge protection device containing at least one heterojunction transistor is disclosed. In another embodiment, an Electrostatic Discharge protection circuit comprises: a first terminal contact 20; an NPN heterojunction bipolar transistor Q2; a PNP bipolar transistor Q1; a base-emitter shunt resistor R2; an emitter of said PNP transistor connected to said first terminal contact; a base of said PNP transistor connected to collector of said NPN transistor; a collector of said PNP transistor connected to a base of said NPN transistor; and an emitter of said NPN transistor connected to a second terminal contact 22, with said base-emitter shunt resistor connected between said base of said NPN transistor and an emitter of said NPN transistor, whereby a low-capacitance device capable of protecting semiconductor devices from electrostatic discharges in excess of 4000 Volts results. Other devices, systems, and methods are also disclosed.

US Patent:

62470361, Jun 12, 2001

Filed:

Jan 21, 1997

Appl. No.:

8/787496

Inventors:

George Landers - Mt. View CA
Earle Jennings - San Jose CA
Tim B. Smith - Dallas TX
Glen Haas - Plano TX

Assignee:

Infinite Technology Corp. - Richardson TX

International Classification:

G06F 1500

US Classification:

708603

Abstract:

A reconfigurable processor includes at least three (3) MacroSequencers (10)-(16) which are configured in an array. Each of the MacroSequencers is operable to receive on a separate one of four buses (18) an input from the other three MacroSequencers and from itself in a feedback manner. In addition, a control bus (20) is operable to provide control signals to all of the MacroSequencers for the purpose of controlling the instruction sequence associated therewith and also for inputting instructions thereto. Each of the MacroSequencers includes a plurality of executable units having inputs and outputs and each for providing an associated execution algorithm. The outputs of the execution units are input to an output selector which selects the outputs for outputs on at least one external output and on at least one feedback path. An input selector (66) is provided having an input for receiving at least one external output and at least the feedback path. These are selected between for input to select ones of the execution units.

US Patent:

55369065, Jul 16, 1996

Filed:

Jul 23, 1993

Appl. No.:

8/097336

Inventors:

Glen R. Haas - Plano TX
John E. Barnett - Mesquite TX
Stephen R. Nelson - Richardson TX
Douglas J. Darrow - Dallas TX
Susan V. Bagen - Dallas TX
Henry Breit - Attleboro MA
James Forster - Barrington RI

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2302

US Classification:

174 524

Abstract:

In one form of the invention, a package for integrated circuits and devices (42), (46) is disclosed, the package including: a package base (44), the base having a first top surface; a layer of material (43) on the first top surface of the base (44) wherein the material (43) is patterned to cover a portion of the base, and wherein the layer of material (43) forms a substrate having a second top surface; a microstrip transmission line (45) on the second top surface; and a plastic encapsulant (50), wherein the encapsulant covers the first top surface of the base.