Geza Myrna B Csanky

US Patent:

42563828, Mar 17, 1981

Filed:

May 3, 1979

Appl. No.:

6/035679

Inventors:

Michael A. Piliavin - Encino CA
Geza Csanky - Sepulveda CA

Assignee:

Hughes Aircraft Company - Culver City CA

International Classification:

G02F 1133

US Classification:

350334

Abstract:

A liquid crystal cell for use in a display and a method for manufacturing such display is disclosed. Each cell of such display includes a membrane which is manufactured by conventional semiconductor processing technology. Such membrane has semiconductor structural support members between which liquid crystal fluid is retained. Such membrane and residual liquid crystal fluid in the cell have substantially the same thermal coefficient of expansion as a silicon integrated circuit chip attached to the rib members. The membrane prevents warpage and deterioration of each liquid crystal cell, maintains uniformity of spacing between structural members of the cell, and enables a high quality cell to be fabricated with accompanying improved cell fabrication yield.

US Patent:

58894314, Mar 30, 1999

Filed:

Jun 26, 1997

Appl. No.:

8/883223

Inventors:

Geza Csanky - Manhattan Beach CA

Assignee:

The Aerospace Corporation - El Segundo CA

International Classification:

G05F 110

US Classification:

327543

Abstract:

A method controls the load currents of current mirror loads of logic circuits, for lowering power dissipation at high frequency clock rates while providing stable output signal logic levels insensitive to operating conditions such as varying external radiation well suited for CMOS circuit operation. The method enables segmented control of logic circuits for powering up operational circuits while powering down dormant circuits for efficient power utilization.

US Patent:

58894306, Mar 30, 1999

Filed:

Jun 26, 1997

Appl. No.:

8/883222

Inventors:

Geza Csanky - Manhattan Beach CA

Assignee:

The Aerospace Corporation - El Segundo CA

International Classification:

G05F 110

US Classification:

327543

Abstract:

A current mirror includes a reference transistor connected between the current source and current transistor and receives a reference voltage level and for providing a mirror voltage to a mirror transistor providing a current load to a driver connected to the mirror transistor of the current mirror for operating a logic circuit in a static current mode offering lower power dissipation at high frequency clock rates and for providing stable output signal logic levels insensitive to operating conditions such as varying external radiation well suited for CMOS circuit operation.

US Patent:

48209996, Apr 11, 1989

Filed:

Sep 11, 1987

Appl. No.:

7/096563

Inventors:

Geza Csanky - Manhattan Beach CA

Assignee:

The Aerospace Corporation - El Segundo CA

International Classification:

H03F 316

US Classification:

330277

Abstract:

A method and apparatus for amplifying signals is disclosed. In one embodiment, the apparatus comprises a first MOSFET having a drain, a source and a gate. The apparatus further comprises a second MOSFET having a drain, a source and a gate. The second MOSFET is a depletion mode device having a substantially greater drain saturation current than the first MOSFET. The drain of the first MOSFET is connected to the source of the second MOSFET through a first conductor, and the source of the first MOSFET is connected to the gate of the second MOSFET through a second conductor. Finally, the apparatus further comprises a conductor for connecting the drain of the second MOSFET to biasing source to apply sufficient voltage to cause saturation of the first and second MOSFETs.