Gerhard G Mueller

Author:

Gerhard Mueller

ISBN #:

0072434880

Author:

Gerhard Mueller

ISBN #:

0256181055

Author:

Gerhard Mueller

ISBN #:

0819450227

Author:

Gerhard Mueller

ISBN #:

3927943029

Author:

Gerhard O. Mueller

ISBN #:

0837708273

Author:

Gerhard O. Mueller

ISBN #:

0837708303

Author:

Gerhard G. Mueller

ISBN #:

0030830400

Author:

Gerhard G. Mueller

ISBN #:

0030899087

US Patent:

6370055, Apr 9, 2002

Filed:

Feb 28, 2001

Appl. No.:

09/795761

Inventors:

David Hanson - Brewster NY
Gerhard Mueller - Wappingers Falls NY
Toshiaki Kirihata - Poughkeepsie NY

Assignee:

Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY

International Classification:

G11C 506

US Classification:

365 63, 365 69, 36523003, 365214, 365 51

Abstract:

There is provided a semiconductor memory having a plurality of memory units. The memory includes a plurality of read write drive (RWD) lines horizontally and/or vertically twisted such that the RWD lines are shared between the plurality of memory units. A plurality of columns is included in each of the plurality of memory units. Each of the plurality of columns is adapted to access the plurality of RWD lines through asymmetrical addressing.

US Patent:

6522171, Feb 18, 2003

Filed:

Jan 11, 2001

Appl. No.:

09/759011

Inventors:

David R. Hanson - Brewster NY
Toshiaki Kirihata - Poughkeepsie NY
Gerhard Mueller - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19096

US Classification:

326 95, 326 98

Abstract:

A dynamic logic circuit having reduced sub-threshold leakage current during standby mode comprises a connection to at least one upper power rail, a connection to a lower power rail, a precharge node, and an output node adapted to be charged to the potential of the upper power rail after a precharge signal is received at the precharge node. A latch on the output node is provided to maintain the potential at the output node, along with at least one input node for receiving at least one evaluation signal to maintain the potential at the output node to the voltage of the upper power rail or reduce the potential at the output node to the potential of the lower power rail. A device is coupled to the output node to set the output node to a potential which minimizes the sub-threshold leakage upon receipt of a standby signal to maintain the potential at the output node at the potential of the upper power rail or at the potential of the lower power rail.

US Patent:

6529054, Mar 4, 2003

Filed:

Oct 22, 1999

Appl. No.:

09/425329

Inventors:

David Russell Hanson - Brewster NY
Gerhard Mueller - Wappingers Falls NY

Assignee:

Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY

International Classification:

H03L 716

US Classification:

327144, 327154, 327288, 327294, 327394, 375354, 375377

Abstract:

A synchronized data capture circuit configured to synchronize capturing of data in a first plurality of data signals with a first plurality of timing signals to output a synchronized data capture signal. The synchronized data capture circuit includes a timer generator having a first timer generator output. The timer generator is coupled to receive the first plurality of timing signals and to serially output on the first timer generator output, as a first high frequency timing pulse stream, first timing pulses responsive to timing pulses of the plurality of timing signals. The first high frequency timing pulse stream has a timing pulse stream frequency that is higher than a timing input frequency associated with one of the first plurality of timing signals. The synchronized data capture circuit also includes first plurality of data driver circuits coupled to receive the first plurality of data signals and the plurality of timing signals. The first plurality of data driver circuits are configured to serially output, as a first high frequency data stream, first data pulses responsive to the timing pulses of the plurality of timing signals and data pulses of the first plurality of data signal.

US Patent:

6668031, Dec 23, 2003

Filed:

Aug 19, 1999

Appl. No.:

09/377588

Inventors:

David Russell Hanson - Brewster NY
Gerhard Mueller - Wappingers Falls NY

Assignee:

Infineon Technologies AG
International Business Machines Corporation - Armonk NY

International Classification:

H04L 700

US Classification:

375355, 327141

Abstract:

A synchronized data capture circuit configured to synchronize capturing of data in a data signal with a timing signal in an integrated circuit. The synchronized data circuit employs voltage signals having a reduced voltage level, the data signal and the timing signal having a first voltage level higher than the reduced voltage level. The synchronized data capture circuit includes a timing driver circuit arranged to receive the timing signal. The timing driver circuit outputs a reduced voltage timing signal having the reduced voltage level. There is included a data driver circuit arranged to receive the data signal and the timing signal, the data driver outputting a reduced voltage clocked data signal having the reduced voltage level. There is further included a data clocking circuit coupled to the timing driver circuit and the data driver circuit. The data clocking circuit is arranged to receive the reduced voltage timing signal and the reduced voltage clocked data signal.

US Patent:

59562340, Sep 21, 1999

Filed:

Jan 20, 1998

Appl. No.:

9/009650

Inventors:

Gerhard M. Mueller - Pleasanton CA

Assignee:

Integrated Device Technology, Inc. - Santa Clara CA

International Classification:

H05K 111

US Classification:

361767

Abstract:

A method and structure for a surface mountable rigid-flex printed circuit board is disclosed. A rigid-flex circuit board is mounted onto a printed circuit board using standard surface mount technology such as ball grid array, pin grid array or solder screen print. The use of rigid-flex board allows tested, burned in components to be used while still allowing a small multiple chip module footprint.

US Patent:

61278785, Oct 3, 2000

Filed:

Jan 5, 1999

Appl. No.:

9/225664

Inventors:

David R. Hanson - Brewster NY
Gerhard Mueller - Wappingers Falls NY

Assignee:

Siemens Aktiengesellschaft - Munich
International Business Machines Corporation - Armonk NY

International Classification:

H03K 1704

US Classification:

327374

Abstract:

A high frequency driver circuit is described. The driver produces increased current flow at its output to decrease charging time, thereby enabling higher frequency operations. Increased current flow is achieved by providing an active control signal that increases the magnitude of the overdrive voltage applied to a driver transistor.

US Patent:

61811653, Jan 30, 2001

Filed:

Mar 9, 1998

Appl. No.:

9/037289

Inventors:

David R. Hanson - Brewster NY
Gerhard Mueller - Wappingers Falls NY

Assignee:

Siemens Aktiengesellschaft - Munich
International Business Machines Corporation - Armonk NY

International Classification:

H03K 190185

US Classification:

326 81

Abstract:

There is disclosed a tri-state buffer circuit for receiving an input signal at a buffer input node and transmitting, responsive to a buffer enable signal, an output signal at a buffer output node. The buffer circuit includes an input stage coupled to the buffer input node. The input stage is configured to receive, when the buffer enable signal is enabled, the input signal. The buffer circuit further includes a level shifter stage coupled to the input stage. The level shifter stage is arranged to output, when the buffer enable signal is enabled, a set of level shifter stage control signals responsive to the input signal. A voltage range of the set of level shifter stage control signals is higher than a voltage range associated with the input signal. The buffer circuit also includes an output stage coupled to the level shifter stage. The output stage is configured to output, when the buffer enable signal is enabled, the output signal on the buffer output node responsive to the set of level shifter stage control signals.

US Patent:

62153498, Apr 10, 2001

Filed:

Mar 9, 1999

Appl. No.:

9/265253

Inventors:

David Russell Hanson - Brewster NY
Gerhard Mueller - Wappingers Falls NY

Assignee:

International Business Machines Corp. - Armonk NY
Infineon Technologies North America Corp. - San Jose CA

International Classification:

H03K 1716

US Classification:

327390

Abstract:

A high performance driver circuit is described. The driver produces increased current flow at its output to decrease charging time. Increased current flow is achieved by providing an overdrive circuit that provides a voltage offset to increase the magnitude of the overdrive voltage.