Georgios I Stamoulis

US Patent:

58382038, Nov 17, 1998

Filed:

Dec 6, 1996

Appl. No.:

8/760905

Inventors:

Georgios Stamoulis - Fremont CA
Yibin Ye - West Lafayette IN

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03L 706
H03B 2800

US Classification:

331 1A

Abstract:

A method and an apparatus for generating oscillating waveforms using adiabatic circuitry. In one embodiment, an LC oscillating circuit generates oscillating waveforms that are replenished with replenishing circuitry. The replenishing circuitry includes enable circuitry and circuitry that reduces short circuit currents that may flow through the replenishing circuit. Furthermore, the pull-up and pull-down devices of the replenishing circuit are gradually turned on and gradually turned off to reduce the introduction of glitches into the oscillating sinusoidal waveform of the oscillating circuit. A control circuit, such as a phase lock loop circuit, is included with the present invention to receive an external clock reference waveform and match the frequency and phase of the oscillating waveform in the oscillating circuit to the external clock reference waveform. Control signals are generated by the phase lock loop circuit to control the pull-up and pull-down devices of the replenishing circuit to adjust the frequency and phase of the oscillating waveform in the oscillating circuit. Accordingly, the frequency and phase of the oscillating waveform may be controlled and adjusted with an external clock reference enabling the disclosed waveform generation circuit to be integrated into a system controlled by an external clock.

US Patent:

58314539, Nov 3, 1998

Filed:

Dec 30, 1996

Appl. No.:

8/777547

Inventors:

Georgios I. Stamoulis - Campbell CA
Junji Sugisawa - Santa Clara CA
Michael Y. Zhang - Palo Alto CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 190948
H03K 19096

US Classification:

326113

Abstract:

A method and apparatus for low power transmission of digital data. A low power data transmission circuit includes a pass gate having parallel-connected n and p-channel CMOS transistors that transmit input data. To reduce power in a first embodiment, a circuit disables the parallel-connected p-channel pass gate transistor except when the input data is high (logical 1). The p-channel pass gate transistor is needed to pass logical 1's without degradation. In the first embodiment, the n-channel pass gate transistor is enabled to transmit the input data on every clock cycle. In a second embodiment, the circuit disables the parallel-connected n-channel pass gate transistor except when the input data is low (logical 0). The n-channel pass gate transistor is needed to pass logical 0's without degradation. In this embodiment, the p-channel pass gate transistor is enabled to transmit the input data on every clock cycle.