George A Fax

US Patent:

6415402, Jul 2, 2002

Filed:

Jan 24, 2001

Appl. No.:

09/768637

Inventors:

James W. Bishop - Newark Valley NY
George A. Fax - Round Rock TX
Robert G. Iseminger - Vestal NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128

US Classification:

714724, 327 18

Abstract:

A programmable timing circuit on an integrated circuit chip for testing the cycle time of functional circuits on the chip. The timing circuit includes a selectable input having at least two sources, one of which is a toggle circuit; a minimally delayed control path including a control latch; a programmable delay path in parallel with the control path and including a sample latch; and a comparator for comparing the state of the control latch and sample latches to provide a signal indicative of the delay path being longer than the control path. A plurality of configuration latches and multiplexers are provided for selecting the input source and routing an input signal through specific delay blocks to control the amount of delay in the delay path.

US Patent:

52108287, May 11, 1993

Filed:

Apr 4, 1990

Appl. No.:

7/504764

Inventors:

Timothy V. Bolan - Endwell NY
Josephine A. Boston - Endicott NY
George A. Fax - Rochester MN
Donald J. Hanrahan - Endwell NY
Bernhard Laubli - Schonaich, DE
David A. Ring - Endicott NY
Alfred T. Rundle - Endwell NY
David J. Shippy - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1314

US Classification:

395200

Abstract:

A plurality of processors are connected to the interprocessor communications facility in the multiprocessing system of the invention. The interprocessor communications facility has arbitration circuitry, mailbox circuitry, and processor interrupt circuitry. The interprocessor communications facility of the invention is centralized and does not require the use of main storage. This enables processors to communicate with each other in a fast and efficient manner. The arbitration circuitry prevents simultaneous access of the interprocessor communications facility by more than one processor, and decodes the commands sent from the processors and routes them to the processor interrupt circuitry or to the mailbox circuitry, depending on the command. The mailbox circuitry of the invention receives messages from sending processors and provides them to the intended receiving processors in a safe and secure manner. The processor interrupt circuitry facilitates the interprocessor communications process by handling interprocessor interrupts.

US Patent:

62198130, Apr 17, 2001

Filed:

Jun 29, 1998

Appl. No.:

9/106959

Inventors:

James W. Bishop - Newark Valley NY
George A. Fax - Round Rock TX
Robert G. Iseminger - Vestal NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

714736

Abstract:

A programmable timing circuit on an integrated circuit chip for testing the cycle time of functional circuits on the chip. The timing circuit includes a selectable input having at least two sources, one of which is a toggle circuit; a minimally delayed control path including a control latch; a programmable delay path in parallel with the control path and including a sample latch; and a comparator for comparing the state of the control latch and sample latches to provide a signal indicative of the delay path being longer than the control path. A plurality of configuration latches and multiplexers are provided for selecting the input source and routing an input signal through specific delay blocks to control the amount of delay in the delay path.