George J Cuan from 10835 Dryden Ave, Cupertino, CA 95014, age 54, Phone: 408 736-8769

Us Patents

Apparatus And Method For Performing Setup Operations In A 3-D Graphics Pipeline Using Unified Primitive Descriptors
view source
US Patent:

6577305, Jun 10, 2003
Filed:

Aug 20, 1999
Appl. No.:

09/378598
Inventors:

Richard E. Hessel - Pleasanton CA
Vaughn T. Arnold - Scotts Valley CA
Jack Benkual - Cupertino CA
George Cuan - Sunnyvale CA
Stephen L. Dodgen - Boulder Creek CA
Emerson S. Fang - Fremont CA
Hengwei Hsu - Fremont CA
Sushma S. Trivedi - Sunnyvale CA
Assignee:

Apple Computer, Inc. - Cupertino CA
International Classification:

G06T 1700
US Classification:

345419, 345420
Abstract:

The present invention provides post tile sorting setup in a tiled graphics pipeline architecture. In particular, the present invention determines a set of clipping points that identify intersections of a primitive with a tile. The mid-pipeline setup unit is adapted to compute a minimum depth value for that part of the primitive intersecting the tile. The mid-pipeline setup unit can be adapted to process primitives with x-coordinates that are screen based and y-coordinates that are tile based. Additionally, to the mid-pipeline setup unit is adapted to represent both line segments and triangles as quadrilaterals, wherein not all of a quadrilaterals vertices are required to describe a triangle.

Graphics Processor With Deferred Shading
view source
US Patent:

6597363, Jul 22, 2003
Filed:

Aug 20, 1999
Appl. No.:

09/378637
Inventors:

Richard E. Hessel - Pleasanton CA
Vaughn T. Arnold - Scotts Valley CA
Jack Benkual - Cupertino CA
Joseph P. Bratt - San Jose CA
George Cuan - Sunnyvale CA
Stephen L. Dodgen - Boulder Creek CA
Emerson S. Fang - Fremont CA
Zhaoyu Gong - Cupertino CA
Thomas Y. Ho - Fremont CA
Hengwei Hsu - Fremont CA
Sidong Li - San Jose CA
Sam Ng - Fremont CA
Matthew N. Papakipos - Menlo Park CA
Jason R. Redgrave - Mountain View CA
Sushma S. Trivedi - Sunnyvale CA
Nathan D. Tuck - San Diego CA
Assignee:

Apple Computer, Inc. - Cupertino CA
International Classification:

G06T 120
US Classification:

345506, 345545, 345563, 345653, 345654
Abstract:

Graphics processors and methods are described that encompass numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures. Embodiments of the invention may include one or more of deferred shading, a bled frame buffer, and multiple-stage hidden surface removal processing, as well as other structures and/or procedures. Embodiments of the present invention are designed to provide high-performance 3D graphics with Phong shading, subpixel anti-aliasing, and texture- and bump-mappings.

Deferred Shading Graphics Pipeline Processor Having Advanced Features
view source
US Patent:

6717576, Apr 6, 2004
Filed:

Aug 20, 1999
Appl. No.:

09/377503
Inventors:

Richard E. Hessel - Pleasanton CA
Vaughn T. Arnold - Scotts Valley CA
Jack Benkual - Cupertino CA
Joseph P. Bratt - San Jose CA
George Cuan - Sunnyvale CA
Stephen L. Dodgen - Boulder Creek CA
Emerson S. Fang - Fremont CA
Zhaoyu Gong - Cupertino CA
Thomas Y. Ho - Fremont CA
Hengwei Hsu - Fremont CA
Sidong Li - San Jose CA
Sam Ng - Fremont CA
Matthew N. Papakipos - Menlo Park CA
Jason R. Redgrave - Mountain View CA
Sushma S. Trivedi - Sunnyvale CA
Nathan D. Tuck - San Diego CA
Shun Wai Go - Milpitas CA
Lindy Fung - Sunnyvale CA
Tuan D. Nguyen - San Jose CA
Joseph P. Grass - Menlo Park CA
Bo Hong - San Jose CA
Abraham Mammen - Pleasanton CA
Abbas Rashid - Fremont CA
Albert Suan-Wei Tsay - Fremont CA
Assignee:

Apple Computer, Inc. - Cupertino CA
International Classification:

G06T 1500
US Classification:

345419, 345506, 345522
Abstract:

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Deferred Shading Graphics Pipeline Processor Having Advanced Features
view source
US Patent:

7167181, Jan 23, 2007
Filed:

Jun 9, 2003
Appl. No.:

10/458493
Inventors:

Richard E. Hessel - Pleasanton CA, US
Vaughn T. Arnold - Scotts Valley CA, US
Jack Benkual - Cupertino CA, US
Joseph P. Bratt - San Jose CA, US
George Cuan - Sunnyvale CA, US
Stephen L. Dodgen - Boulder Creek CA, US
Emerson S. Fang - Fremont CA, US
Zhaoyu Gong - Cupertino CA, US
Thomas Y. Ho - Fremont CA, US
Hengwei Hsu - Fremont CA, US
Sidong Li - San Jose CA, US
Sam Ng - Fremont CA, US
Matthew N. Papakipos - Menlo Park CA, US
Jason R. Redgrave - Mountain View CA, US
Sushma S. Trivedi - Sunnyvale CA, US
Nathan D. Tuck - San Diego CA, US
Shun Wai Go - Milpitas CA, US
Lindy Fung - Sunnyvale CA, US
Tuan D. Nguyen - San Jose CA, US
Joseph P. Grass - Menlo Park CA, US
Bo Hong - San Jose CA, US
Abraham Mammen - Pleasanton CA, US
Abbas Rashid - Fremont CA, US
Albert Suan-Wei Tsay - Fremont CA, US
Assignee:

Apple Computer, Inc. - Cupertino CA
International Classification:

G06T 1/20
G06T 15/40
G09G 5/00
US Classification:

345506, 345421, 345613, 345614
Abstract:

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Deferred Shading Graphics Pipeline Processor Having Advanced Features
view source
US Patent:

7808503, Oct 5, 2010
Filed:

Dec 19, 2006
Appl. No.:

11/613093
Inventors:

Richard E. Hessel - Pleasanton CA, US
Vaughn T. Arnold - Scotts Valley CA, US
Jack Benkual - Cupertino CA, US
Joseph P. Bratt - San Jose CA, US
George Cuan - Sunnyvale CA, US
Stephen L. Dodgen - Boulder Creek CA, US
Emerson S. Fang - Fremont CA, US
Zhaoyu Gong - Cupertino CA, US
Thomas Y. Yo - Fremont CA, US
Hengwei Hsu - Fremont CA, US
Sidong Li - San Jose CA, US
Sam Ng - Fremont CA, US
Matthew N. Papakipos - Menlo Park CA, US
Jason R. Redgrave - Mountain View CA, US
Sushma S. Trivedi - Sunnyvale CA, US
Nathan D. Tuck - San Diego CA, US
Shun Wai Go - Milpitas CA, US
Lindy Fung - Sunnyvale CA, US
Tuan D. Nguyen - San Jose CA, US
Joseph P. Grass - Menlo Park CA, US
Bo Hong - San Jose CA, US
Abraham Mammen - Pleasanton CA, US
Abbas Rashid - Fremont CA, US
Albert Suan-Wei Tsay - Fremont CA, US
Assignee:

Apple Inc. - Cupertino CA
International Classification:

G06T 1/20
G06T 15/00
G06T 15/10
US Classification:

345506, 345419, 345427
Abstract:

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Deferred Shading Graphics Pipeline Processor
view source
US Patent:

62688758, Jul 31, 2001
Filed:

Aug 4, 2000
Appl. No.:

9/632293
Inventors:

Jerome F. Duluk - Palo Alto CA
Richard E. Hessel - Pleasanton CA
Vaughn T. Arnold - Scotts Valley CA
Jack Benkual - Cupertino CA
Joseph P. Bratt - San Jose CA
George Cuan - Sunnyvale CA
Stephen L. Dodgen - Boulder Creek CA
Emerson S. Fang - Fremont CA
Zhaoyu Gong - Cupertino CA
Thomas Y. Ho - Fremont CA
Hengwei Hsu - Fremont CA
Sidong Li - San Jose CA
Sam Ng - Fremont CA
Matthew N. Papakipos - Menlo Park CA
Jason R. Redgrave - Mountain View CA
Sushma S. Trivedi - Sunnyvale CA
Nathan D. Tuck - San Diego CA
Assignee:

Apple Computer, Inc. - Cupertino CA
International Classification:

G06T 120
US Classification:

345506
Abstract:

Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is a Deferred Shading Graphics Processor (DSGP) comprising an AGP interface, a command fetch & decode (2000), a geometry unit (3000), a mode extraction (4000) and polygon memory (5000), a sort unit (6000) and sort memory (7000), a setup unit (8000), a cull unit (9000), a mode injection (10000), a fragment unit (11000), a texture (12000) and texture memory (13000) a phong shading (14000), a pixel unit (15000), a backend unit (1600) coupled to a frame buffer (17000). Other embodiments need not include all of these functional units, and the structures and methods of these units are applicable to other computational processes and systems as well as deferred and non-deferred shading graphical processors.

Deferred Shading Graphics Pipeline Processor
view source
US Patent:

62295535, May 8, 2001
Filed:

Aug 20, 1999
Appl. No.:

9/378299
Inventors:

Jerome F. Duluk - Palo Alto CA
Richard E. Hessel - Pleasanton CA
Vaughn T. Arnold - Scotts Valley CA
Jack Benkual - Cupertino CA
Joseph P. Bratt - San Jose CA
George Cuan - Sunnyvale CA
Stephen L. Dodgen - Boulder Creek CA
Emerson S. Fang - Fremont CA
Zhaoyu Gong - Cupertino CA
Thomas Y. Ho - Fremont CA
Hengwei Hsu - Fremont CA
Sidong Li - San Jose CA
Sam Ng - Fremont CA
Matthew N. Papakipos - Menlo Park CA
Jason R. Redgrave - Mountain View CA
Sushma S. Trivedi - Sunnyvale CA
Nathan D. Tuck - San Diego CA
Assignee:

Apple Computer, Inc. - Cupertino CA
International Classification:

G06T 120
US Classification:

345506
Abstract:

Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is Deferred Shading Graphics Processor (DSGP) comprising an AGP interface, a command fetch decode (2000), a geometry unit (3000), a mode extraction (4000) and polygon memory (5000), a sort unit (6000) and sort memory (7000), a setup unit (8000), a cull unit (9000), a mode injection (10000), a fragment unit (11000), a texture (12000) and texture memory (13000) a phong shading (14000), a pixel unit (15000), a backend unit (1600) coupled to a frame buffer (17000). Other embodiments need not include all of these functional units, and the structures and methods of these units are applicable to other computational processes and systems as well as deferred and non-deferred shading graphical processors.