Geoffrey Kuen Yung

US Patent:

7685372, Mar 23, 2010

Filed:

Jan 13, 2005

Appl. No.:

11/034677

Inventors:

Hong-Yi Chen - Fremont CA, US
Geoffrey K. Yung - Belmont CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G06F 12/00

US Classification:

711141, 711122

Abstract:

A digital system that connects to a bus that employs physical addresses comprises a processing core. A level one (L1) cache communicates with the processing core. A level two (L2) cache communicates with the L1 cache. Both the L1 cache and the L2 cache are indexed by virtual addresses and tagged with virtual addresses. A bus unit communicates with the L2 cache and with the bus.

US Patent:

7730261, Jun 1, 2010

Filed:

Aug 21, 2006

Appl. No.:

11/507880

Inventors:

Geoffrey K. Yung - Belmont CA, US
Chia-Hung Chien - Sunnyvale CA, US

Assignee:

Marvell International Ltd.

International Classification:

G06F 12/00

US Classification:

711130

Abstract:

A multiprocessing system includes, in part, a multitude of processing units each in direct communication with a bus, a multitude of memory units in direct communication with the bus, and at least one shared memory not in direct communication with the bus but directly accessible to the plurality of processing units. The shared memory may be a cache memory that stores instructions and/or data. The shared memory includes a multitude of banks, a first subset of which may store data and a second subset of which may store instructions. A conflict detection block resolves access conflicts to each of the of the banks in accordance with a number of address bits and a predefined arbitration scheme. The conflict detection block provides each of the processing units with sequential access to the banks during consecutive cycles of a clock signal.

US Patent:

7730285, Jun 1, 2010

Filed:

Aug 2, 2006

Appl. No.:

11/497805

Inventors:

Hong-Yi Chen - Fremont CA, US
Richard Lee - Hillsborough NJ, US
Geoffrey K. Yung - Belmont CA, US
Jensen Tjeng - Sunnyvale CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G06F 9/312

US Classification:

712218, 712217

Abstract:

A data processing system includes a plurality of functional units that selectively execute instructions. A register file includes a plurality of registers that store data corresponding to the instructions. A reorder buffer communicates with the register file and stores the data, includes at least one bypassable buffer location, and includes at least one non-bypassable buffer location.

US Patent:

7949833, May 24, 2011

Filed:

Mar 22, 2010

Appl. No.:

12/728583

Inventors:

Hong-Yi Chen - Fremont CA, US
Geoffrey K. Yung - Belmont CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G06F 12/00

US Classification:

711141, 711122

Abstract:

A digital system that connects to a bus that employs physical addresses comprises a processing core. A level one (L1) cache communicates with the processing core. A level two (L2) cache communicates with the L1 cache. Both the L1 cache and the L2 cache are indexed by virtual addresses and tagged with virtual addresses. A bus unit communicates with the L2 cache and with the bus.

US Patent:

7984246, Jul 19, 2011

Filed:

Apr 7, 2010

Appl. No.:

12/755893

Inventors:

Geoffrey K. Yung - Belmont CA, US
Chia-Hung Chien - Sunnyvale CA, US

Assignee:

Marvell International Ltd.

International Classification:

G06F 12/00

US Classification:

711147

Abstract:

A multiprocessing system includes, in part, a multitude of processing units each in direct communication with a bus, a multitude of memory units in direct communication with the bus, and at least one shared memory not in direct communication with the bus but directly accessible to the plurality of processing units. The shared memory may be a cache memory that stores instructions and/or data. The shared memory includes a multitude of banks, a first subset of which may store data and a second subset of which may store instructions. A conflict detection block resolves access conflicts to each of the of the banks in accordance with a number of address bits and a predefined arbitration scheme. The conflict detection block provides each of the processing units with sequential access to the banks during consecutive cycles of a clock signal.

US Patent:

8347034, Jan 1, 2013

Filed:

Jan 13, 2005

Appl. No.:

11/034846

Inventors:

Hong-Yi Chen - Fremont CA, US
Geoffrey K. Yung - Belmont CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G06F 12/00
G06F 13/00

US Classification:

711118, 711104, 711122, 711144

Abstract:

A computer cache for a memory comprises a data random-access memory (RAM) containing a plurality of cache lines. Each of the cache lines stores a segment of the memory. A tag RAM contains a plurality of address tags that correspond to the cache lines. A valid RAM contains a plurality of validity values that correspond to the cache lines. The valid RAM is stored separately from the tag RAM and the data RAM. The valid RAM is selectively independently clearable. A hit module determines whether data is stored in the computer cache based upon the valid RAM and the tag RAM.

US Patent:

8621152, Dec 31, 2013

Filed:

Dec 21, 2012

Appl. No.:

13/724864

Inventors:

- Hamilton, BM
Geoffrey Yung - Belmont CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G06F 12/00
G06F 13/00

US Classification:

711118, 711154, 711200

Abstract:

A system comprising a processor, a first cache, and a second cache. The processor is configured to perform a processing task according to data stored in a main memory and output a command associated with the processing task. The first cache is located between the processor and the main memory and is configured to store a first portion of the data stored in the main memory and provide a first indication of whether the command has been completed at the first cache. The second cache is located between the first cache and the main memory and is configured to store a second portion of the data stored in the main memory and provide a second indication of whether the command has been completed at the second cache. The processor is configured to perform the processing task in response to receiving both the first indication and the second indication.

US Patent:

7096345, Aug 22, 2006

Filed:

Sep 26, 2003

Appl. No.:

10/672774

Inventors:

Hong-Yi Hubert Chen - Fremont CA, US
Richard Yen-Ching Lee - Hillsborough NJ, US
Geoffrey Yung - Belmont CA, US
Jensen Tjeng - Sunnyvale CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G06F 9/30

US Classification:

712218, 712217

Abstract:

A data processing system for executing a plurality of instructions having a prescribed program order comprises a register file, a reorder buffer, and a plurality of functional units. The register file includes a plurality of registers to store data. The reorder buffer includes N buffer locations of which M buffer locations are bypassable and N−M buffer locations are non-bypassable, wherein N and M are integers and N>M. Each functional unit is capable of executing instructions regardless of the prescribed program order. The reorder buffer temporarily stores data corresponding to the plurality of instructions. When data of one of the plurality of instructions to be executed by a corresponding one of the plurality of functions units is temporarily stored in one of the M bypassable buffer locations, the reorder buffer transfers the data in one of the bypassable M buffer locations to the corresponding one of the functional units in order to execute the instruction. The register file also stores data corresponding to retired ones of the plurality of instructions.