Gene T Sluss

US Patent:

7069522, Jun 27, 2006

Filed:

May 28, 2004

Appl. No.:

10/856520

Inventors:

Gene T. Sluss - Pleasanton CA, US
Deepak D. Sherlekar - Cupertino CA, US
Tushar R. Gheewala - Los Altos CA, US

Assignee:

Virage Logic Corporation - Fremont CA

International Classification:

G06F 17/50

US Classification:

716 1, 716 10, 716 11, 716 12

Abstract:

Various methods and apparatuses are described in which a volatile latch circuit. The volatile latch circuit may have a master latch sub circuit coupled to a slave latch sub circuit. The slave latch sub circuit maintains the logic state stored by the volatile latch circuit. The slave sub circuit may connect to a first power trace that continuously provides a first voltage potential to the slave latch sub circuit even during a sleep mode. The master latch sub circuit may connect to a second power trace that provides a second voltage potential to the master latch sub circuit that is switchably turned off during the sleep mode.

US Patent:

7219324, May 15, 2007

Filed:

Feb 13, 2004

Appl. No.:

10/779194

Inventors:

Deepak D. Sherlekar - Cupertino CA, US
Gene Sluss - Pleasanton CA, US
Tushar Gheewala - Los Altos CA, US

Assignee:

Virage Logic Corporation - Fremont CA

International Classification:

G06F 17/50

US Classification:

716 12, 716 13, 716 14, 716 15, 716 16

Abstract:

Various methods and apparatuses are described in which an integrated circuit is organized into rows and columns of macro cells having a layout architecture that includes at least two metal layers and a plurality of traces carrying three or more different potentials of voltage routed by the metal layers. A first, a second, and a third adjacent metal layers extend across the integrated circuit. The first metal layer may be located between the second metal layer and the layer of the macro cells. The second metal layer may be located between the third metal layer and the first metal layer. The third metal layer may be orientated orthogonal to the second metal layer. The plurality of traces carry three or more different potentials of voltage and are routed in the metal layers. A first power trace supplies a VDD voltage potential. A second power trace supplies a VSS voltage potential.

US Patent:

7603634, Oct 13, 2009

Filed:

Apr 10, 2006

Appl. No.:

11/401806

Inventors:

Gene T. Sluss - Pleasanton CA, US
Deepak D. Sherlekar - Cupertino CA, US
Tushar R. Gheewala - Los Altos CA, US

Assignee:

Virage Logic Corporation - Fremont CA

International Classification:

G06F 17/50

US Classification:

716 1, 716 12

Abstract:

An apparatus for a volatile latch circuit. The volatile latch circuit may have a master latch sub circuit coupled to a slave latch sub circuit. The slave latch sub circuit maintains the logic state stored by the volatile latch circuit. The slave sub circuit may connect to a first power trace that continuously provides a first voltage potential to the slave latch sub circuit even during a sleep mode. The master latch sub circuit may connect to a second power trace that provides a second voltage potential to the master latch sub circuit that is switchably turned off during the sleep mode.

US Patent:

8132142, Mar 6, 2012

Filed:

Apr 11, 2007

Appl. No.:

11/734202

Inventors:

Deepak D. Sherlekar - Cupertino CA, US
Gene Sluss - Cupertino CA, US
Tushar Gheewala - Los Altos CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716127, 716120, 716133, 357534

Abstract:

Various methods and apparatuses are described in which an integrated circuit is organized into rows and columns of macro cells having a layout architecture that includes at least two metal layers and a plurality of traces carrying three or more different potentials of voltage routed by the metal layers. A first, a second, and a third adjacent metal layers extend across the integrated circuit. The plurality of traces carry three or more different potentials of voltage and are routed in the metal layers. A first power trace supplies a VDD voltage potential. A second power trace supplies a VSS voltage potential. A third power trace supplies a third voltage potential to support sleep modes and retain data during sleep modes. All three power supply traces connect to one or more transistors in a first macro cell.

US Patent:

8392862, Mar 5, 2013

Filed:

Jan 23, 2007

Appl. No.:

11/657228

Inventors:

Oscar Siguenza - San Jose CA, US
Duane Breid - Lakeville MN, US
Gene Sluss - Pleasanton CA, US
Deepak Sherlekar - Cupertino CA, US
Mike Colwell - Morgan Hill CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716120

Abstract:

Various methods and apparatuses are described for a power distribution structure. In an embodiment, an integrated circuit contains power gating cells that each contain Metal Oxide Semiconductor (MOS) device switches located relative in the power distribution structure to power up and down a block of logic containing a plurality of individual cells using these MOS device switches. The MOS device switches can be tuned to requirements of a target block of logic in order to meet its optimal voltage drop requirements during its active operational state while minimizing leakage current in its off state.

US Patent:

20130200945, Aug 8, 2013

Filed:

Feb 1, 2013

Appl. No.:

13/757617

Inventors:

Duane Breid - Lakeville MN, US
Gene Sluss - Pleasanton CA, US
Deepak Sherlekar - Cupertino CA, US
Mike Colwell - Morgan Hill CA, US

Assignee:

SYNOPSYS, INC. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

327544, 716120

Abstract:

Various methods and apparatuses are described for a power distribution structure. In an embodiment, an integrated circuit contains power gating cells that each contain Metal Oxide Semiconductor (MOS) device switches located relative in the power distribution structure to power up and down a block of logic containing a plurality of individual cells using these MOS device switches. The MOS device switches can be tuned to requirements of a target block of logic in order to meet its optimal voltage drop requirements during its active operational state while minimizing leakage current in its off state.

US Patent:

47302739, Mar 8, 1988

Filed:

Apr 3, 1986

Appl. No.:

6/847974

Inventors:

Gene T. Sluss - Chippewa Falls WI

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 1700
G11C 2900

US Classification:

365 96

Abstract:

A Programmable Read Only Memory (PROM) and an on-chip programmability verification circuit is provided that allows for the verification of the programmability of lateral fuses. The PROM comprises a plurality of word lines, a plurality of bit lines, and a plurality of fuses, wherein each of the fuses are uniquely coupled between one of the word lines and one of the bit lines. A sense amplifier is coupled between each of the word lines and an output terminal. One each of a plurality of variable voltage current sources having a test voltage applied thereto is coupled to one of the sense amplifiers for providing a current to the sense amplifier, and in turn to the word line and fuse, wherein the resistance of the fuse in relation to a nominal value may be determined by comparing the test voltage and an output voltage on the output terminal.