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Geetanjali C Asuri

age ~47

from San Diego, CA

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Also known as:
  • Geetanjali Chawla Asuri
  • Geetanjali Challa
  • Geetanjali Chawla
  • Challa Challa
  • Greetanjal Chawla Asuri
  • I Chawla Asuri
Phone and address:
12843 Corbett Ct, San Diego, CA 92130
858 414-2133
Related to:
Connected to:

Geetanjali Asuri Phones & Addresses

  • 12843 Corbett Ct, San Diego, CA 92130 • 858 414-2133
  • 14796 Carmel Ridge Rd, San Diego, CA 92128
  • Irvine, CA
  • Oak Park, CA
  • Encino, CA

Work

  • Company:
    Nxp semiconductors
    Aug 2008
  • Position:
    Design engg manager

Education

  • Degree:
    MS
  • School / High School:
    University of California, Los Angeles
    1999 to 2001
  • Specialities:
    Electrical Engineering

Skills

Ic • Mixed Signal • Semiconductors • Asic • Soc • Analog Circuit Design • Analog • Integrated Circuit Design • Circuit Design • Eda • Cmos • Verilog • Digital Signal Processors

Industries

Semiconductors

Us Patents

  • Signal Slew Rate Control For Image Sensors

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  • US Patent:
    20060006915, Jan 12, 2006
  • Filed:
    Jul 12, 2004
  • Appl. No.:
    10/887891
  • Inventors:
    Hai Yan - Fontana CA, US
    Chiajen Lee - Irvine CA, US
    Geetanjali Asuri - Irvine CA, US
    Tien-Min Miao - Alhambra CA, US
    Siri Eikedal - Los Angeles CA, US
    Christopher Zeleznik - Fullerton CA, US
    Gennadiy Agranov - Boise ID, US
  • International Classification:
    H03K 3/017
  • US Classification:
    327175000
  • Abstract:
    An imager with a slew rate control circuit that uses multiple digital control signals to control the rising and falling slew rates of boosted signals, such as transistor gate signals, and/or supply voltages used by an imager or other device. By using digital signals, the invention provides slew rate control that is less affected by power supply, temperature and process variations.

Resumes

Geetanjali Asuri Photo 1

Geetanjali Chawla Asuri

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Location:
3135 north Wilke Rd, Arlington Heights, IL 60004
Industry:
Semiconductors
Work:
NXP Semiconductors since Aug 2008
Design Engg Manager
Conexant 2004 - 2008
Group Leader, Engg
Micron Technology 2002 - 2004
Senior Design Engineer
Education:
University of California, Los Angeles 1999 - 2001
MS, Electrical Engineering Birla Institute of Technology and Science 1995 - 1999
BE (Hons), Electrical Engineering
Skills:
Ic
Mixed Signal
Semiconductors
Asic
Soc
Analog Circuit Design
Analog
Integrated Circuit Design
Circuit Design
Eda
Cmos
Verilog
Digital Signal Processors
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