Gaurav Shrivastav

US Patent:

8555232, Oct 8, 2013

Filed:

Feb 28, 2011

Appl. No.:

13/036308

Inventors:

Suparn Vats - Fremont CA, US
Gaurav Shrivastav - Sunnyvale CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 17/50

US Classification:

716126, 716110, 716130, 716132

Abstract:

Systems and methods for wire routing using virtual landing pads (VLPs) are described. In an embodiment, a method includes routing a wiring path between an output of a first circuit component and a VLP that represents an input of a second circuit component. For example, the VLP may have an area larger than the area of a physical pin of the second circuit component. The method may also include identifying a connection point on the VLP that is separated from an actual terminal of the second circuit, and completing the path between the connection point and the actual terminal. In some embodiments, the output of the first circuit component may also be represented by its own VLP. As such, systems and methods described herein may allow a circuit designer to perform routing procedures in a complex, highly integrated circuit, while reducing the circuit's overall capacitance and associated power consumption.