Gary Thomas Torgusen
age ~58
from Superior, CO
- Also known as:
-
- Gary T Torgusen
- Gary A Torgusen
- Cheysan Veliz
- Gary Thomas N
Gary Torgusen Phones & Addresses
- Superior, CO
- Boulder, CO
- St Petersburg, FL
- Lutz, FL
- Tampa, FL
- Superior, CO
Resumes
Staff Asic Design Engineer
view sourceLocation:
Canton, CT
Industry:
Semiconductors
Work:
Marvell since Jul 2007
Staff ASIC Design Engineer
Agere Systems Sep 2003 - Jul 2007
SOC Design Engineer
Conexant - Boulder, CO Aug 1999 - Sep 2002
Asic Design Engineer
Honeywell Aerospace 1995 - 1999
ASIC Design Engineer
Staff ASIC Design Engineer
Agere Systems Sep 2003 - Jul 2007
SOC Design Engineer
Conexant - Boulder, CO Aug 1999 - Sep 2002
Asic Design Engineer
Honeywell Aerospace 1995 - 1999
ASIC Design Engineer
Education:
Georgia Institute of Technology 1993 - 1995
MSEE, Biomedical/Electromagnetics Florida Institute of Technology 1989 - 1992
BSEE, Electrical Engineering Florida Institute of Technology 1989 - 1992
BSCP, Computer Engineering
MSEE, Biomedical/Electromagnetics Florida Institute of Technology 1989 - 1992
BSEE, Electrical Engineering Florida Institute of Technology 1989 - 1992
BSCP, Computer Engineering
Skills:
Asic
Static Timing Analysis
Ncsim
Physical Design
Timing Closure
Verilog
Soc
Tcl
Vbscript
Clock Tree Synthesis
Physical Verification
Logic Synthesis
Formal Verification
Methodology
Functional Verification
Dft
System on A Chip
Static Timing Analysis
Ncsim
Physical Design
Timing Closure
Verilog
Soc
Tcl
Vbscript
Clock Tree Synthesis
Physical Verification
Logic Synthesis
Formal Verification
Methodology
Functional Verification
Dft
System on A Chip
Interests:
Myhabit
Honeywell Aerospace
Honeywell Aerospace
Staff Asic Design Engineer At Marvell
view sourcePosition:
Staff ASIC Design Engineer at Marvell
Location:
Greater Denver Area
Industry:
Computer Hardware
Work:
Marvell since Jul 2007
Staff ASIC Design Engineer
Agere Systems Sep 2003 - Jul 2007
SOC Design Engineer
Conexant - Boulder, CO Aug 1999 - Sep 2002
Asic Design Engineer
Honeywell Aerospace 1995 - 1999
ASIC Design Engineer
Staff ASIC Design Engineer
Agere Systems Sep 2003 - Jul 2007
SOC Design Engineer
Conexant - Boulder, CO Aug 1999 - Sep 2002
Asic Design Engineer
Honeywell Aerospace 1995 - 1999
ASIC Design Engineer
Education:
Georgia Institute of Technology 1993 - 1995
MSEE, Biomedical/Electromagnetics Florida Institute of Technology 1989 - 1992
BSEE, Electrical Engineering Florida Institute of Technology 1989 - 1992
BSCP, Computer Engineering
MSEE, Biomedical/Electromagnetics Florida Institute of Technology 1989 - 1992
BSEE, Electrical Engineering Florida Institute of Technology 1989 - 1992
BSCP, Computer Engineering
Skills:
ASIC
Static Timing Analysis
NCSim
Physical Design
Timing Closure
Verilog
SoC
TCL
VBScript
Clock Tree Synthesis
Physical Verification
Logic Synthesis
Formal Verification
Methodology
Static Timing Analysis
NCSim
Physical Design
Timing Closure
Verilog
SoC
TCL
VBScript
Clock Tree Synthesis
Physical Verification
Logic Synthesis
Formal Verification
Methodology
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