Garret R Davey

US Patent:

20090248919, Oct 1, 2009

Filed:

Mar 25, 2008

Appl. No.:

12/054988

Inventors:

Jerzy Szwagrzyk - Monument CO, US
Garret Davey - Colorado Springs CO, US
Jeffrey K. Whitt - Colorado Springs CO, US

International Classification:

G06F 3/00

US Classification:

710 52

Abstract:

Disclosed is a pre-fetch system in which data blocks are transferred between a RAM and an interface . Data can be read eight, four, or twice as fast using the pre-fetch technique. Data is stored in a pre-fetch buffer for immediate access and use.

US Patent:

20090248937, Oct 1, 2009

Filed:

Mar 26, 2008

Appl. No.:

12/079371

Inventors:

Richard I. Solomon - Colorado Springs CO, US
Jeffrey K. Whitt - Colorado Springs CO, US
Eugene Saghi - Colorado Springs CO, US
Garret Davey - Colorado Springs CO, US

International Classification:

G06F 13/00

US Classification:

710300

Abstract:

An adapter card for testing the functionality of a particular interface configuration may include an interface core. The interface core may comprise an electric circuit including electronic components and control logic for interfacing with an information handling system device. The adapter card may include a front end data channel coupled with the interface core for transmitting data between the electronic components and the information handling system device. The adapter card may include firmware for setting an indicator and causing the control logic to report a memory requirement to the information handling system device larger than a programmed memory space expected by the control logic.

US Patent:

20200117629, Apr 16, 2020

Filed:

Dec 16, 2019

Appl. No.:

16/715109

Inventors:

- San Jose CA, US
Craig DeSimone - Dacula GA, US
Garret Davey - Cumming GA, US
Yue Yu - Johns Creek GA, US
Roland Knaack - Suwanee GA, US
Scott Herrington - Suwanee GA, US

International Classification:

G06F 13/40
G06F 13/42
G11C 7/10
G11C 11/4096
G11C 7/22
G06F 13/16
G11C 5/04
G11C 11/4076
G11C 11/4093

Abstract:

An apparatus includes a control circuit comprising (i) a first differential data strobe input/output circuit having a first set of driver and termination control inputs and (ii) a second differential data strobe input/output circuit having a second set of driver and termination control inputs. The first and the second sets of driver and termination control inputs are independently programmable. The first and the second differential data strobe input/output circuits operate in a first mode when the first differential data strobe input/output circuit is connected to a first memory device having a first data width and the second differential data strobe input/output circuit is connected to a second memory device having the first data width. The first and the second differential data strobe input/output circuits operate in a second mode when the first differential data strobe input/output circuit and the second differential data strobe input/output circuit are connected in parallel to a single memory device having a second data width.

US Patent:

20190129879, May 2, 2019

Filed:

Aug 9, 2018

Appl. No.:

16/059287

Inventors:

- San Jose CA, US
Craig DeSimone - Dacula GA, US
Garret Davey - Cumming GA, US
Yue Yu - Johns Creek GA, US
Roland Knaack - Suwanee GA, US
Scott Herrington - Suwanee GA, US

International Classification:

G06F 13/40
G06F 13/42
G06F 13/16
G11C 11/4096
G11C 7/10
G11C 7/22

Abstract:

An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to operate with the memory devices having a first data width in a first mode and with the memory devices having a second data width in a second mode. The control circuit may be configured to implement two differential data strobe input/output circuits. The differential data strobe input/output circuits each may have driver and termination control inputs that are independently programmable. The differential data strobe input/output circuits may be configured to be connected in parallel when the control circuit is operating in the second mode.