Gabor T Reizik

US Patent:

6958594, Oct 25, 2005

Filed:

Jan 21, 2004

Appl. No.:

10/762650

Inventors:

Richard Redl - Farvagny-le-Petit, CH
Yuxin Li - Santa Clara CA, US
Gabor Reizik - Dublin CA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G05F001/40

US Classification:

323282, 323284

Abstract:

A switched noise filter circuit for DC-DC converters which use the instantaneous output voltage to establish the converter's duty ratio. The converter cycles the switching element on and off for time intervals Tand T, respectively. A switching control circuit includes a filter capacitance connected between the feedback node and ground, and a comparator which compares a feedback voltage Vwith a fixed voltage V; at least one of Tand Tis a “modulated” interval which is terminated when Vcrosses Vdue to the discharge of the filter capacitance. A switched noise filter circuit applies an offset voltage to Vduring at least one of T, and T, with the offset voltage disconnected from Vby the beginning of the modulated interval or shortly thereafter. When the offset voltage is properly applied, the effect of extraneous electromagnetic noise coupled into Vis reduced.

US Patent:

6961396, Nov 1, 2005

Filed:

Jan 26, 2001

Appl. No.:

09/770543

Inventors:

Jonathan M. Audy - Los Gatos CA, US
Gabor Reizik - Dublin CA, US
Richard Redl - Farvagny-le-Petit, CH
Brian P. Erisman - Carlsbad CA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H04B001/10

US Classification:

375351, 455223

Abstract:

A digital blanking circuit allows a first digital input signal transition to be passed on to a following stage, but prohibits the passing of subsequent transitions for a predetermined blanking interval. One embodiment of the present invention employs rising edge and falling edge latches, the inputs of which receive the digital input signal and the outputs of which are connected to a two-to-one multiplexer. The mux output is connected to a blanking interval circuit, which is triggered to begin timing a blanking interval by a multiplexer output transition. The blanking interval circuit provides outputs which control the latches and selects the latch output to be transferred to the multiplexer output such that the multiplexer output is prevented from transitioning during a blanking interval. An “adaptive” blanking circuit is also described in which the blanking interval is terminated when the transition which triggered the start of the blanking interval propagates through an entire signal path, such that the blanking interval is automatically adjusted to be the same as the signal path delay.

US Patent:

7466894, Dec 16, 2008

Filed:

Mar 1, 2006

Appl. No.:

11/367003

Inventors:

Tod F. Schiff - Portland OR, US
Rodney J. Goldhammer - Oregon City OR, US
Gabor T. Reizik - Dublin CA, US

Assignee:

Semiconductor Components Industries, L.L.C. - Phoenix AZ

International Classification:

G02B 6/00
G05F 1/00

US Classification:

385147, 323282

Abstract:

A power supply monitoring system generates a monitor signal having information on more than one aspect of the power supply output. In one example embodiment, the monitor signal may be implemented as a square wave in which the duty cycle is proportional to output current, the peak amplitude is proportional to output voltage, and the average value is equal to output power.

US Patent:

20140049232, Feb 20, 2014

Filed:

Jul 9, 2013

Appl. No.:

13/937943

Inventors:

Gang Chen - Taipo, HK
Chunbo Liu - San Jose CA, US
Gabor Reizik - Dublin CA, US

Assignee:

SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC - PHOENIX AZ

International Classification:

G05F 1/10

US Classification:

323234

Abstract:

In one embodiment, a method of forming a ripple suppressor circuit includes a configuring the ripple suppressor circuit to receive a first signal that is representative of a requested voltage and a second signal that is a filtered value of the first signal. The method also includes configuring the ripple suppressor circuit to determine a peak value of the second signal responsively to the first signal and to determine a minimum value of the second signal responsively to the first signal. The method may also include configuring the ripple suppressor circuit to form an average value of the peak value and the minimum value.

US Patent:

20140049240, Feb 20, 2014

Filed:

Aug 2, 2013

Appl. No.:

13/958429

Inventors:

Gang Chen - Taipo, HK
Gabor Reizik - Dublin CA, US
Paul J. Harriman - Belfair WA, US
KISUN LEE - Hwasungsi, KR

Assignee:

SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC - PHOENIX AZ

International Classification:

G05F 1/10

US Classification:

323282

Abstract:

In one embodiment, a method of forming a multi-channel power supply controller includes forming a plurality of channels configured to regulate an output voltage between first and second values, configuring the controller to select a channel that has a lowest current value and initiate forming a drive signal for that channel responsively to the output voltage having a value that is less than the first value, configuring a reset circuit for each channel to terminate the respective drive signal responsively to at least the output voltage having a value greater than the first value.

US Patent:

60641878, May 16, 2000

Filed:

Feb 12, 1999

Appl. No.:

9/249266

Inventors:

Richard Redl - Farvagny-le-Petit, CH
Brian P. Erisman - Sunnyvale CA
Jonathan M. Audy - San Jose CA
Gabor Reizik - Pleasanton CA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G05F 140

US Classification:

323285

Abstract:

A method and circuit enable a voltage regulator to employ the smallest possible output capacitor that allows the regulator's output voltage to be maintained within specified boundaries for large bidirectional step changes in load current. This is achieved by employing an output capacitor which has a combination of the largest possible equivalent series resistance (ESR) and lowest possible capacitance that ensures that the peak voltage deviation for a step change in load current is no greater than the maximum allowed, and by compensating the regulator to ensure a response that is flat after the occurrence of the peak deviation. The invention is applicable to both switching and linear voltage regulators.

US Patent:

62292927, May 8, 2001

Filed:

Apr 25, 2000

Appl. No.:

9/557785

Inventors:

Richard Redl - Farvagny-le-Petit, CH
Brian P. Erisman - San Francisco CA
Jonathan M. Audy - San Jose CA
Gabor Reizik - Pleasanton CA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G05F 140

US Classification:

323285

Abstract:

A method and circuit enable a voltage regulator to employ the smallest possible output capacitor that allows the regulator's output voltage to be maintained within specified boundaries for large bidirectional step changes in load current. This is achieved with a technique referred to as "optimal voltage positioning", which keeps the output voltage within the specified boundaries while employing an output capacitor which has a combination of the largest possible equivalent series resistance (ESR) and lowest possible capacitance that ensures that the peak voltage deviation for a step change in load current is no greater than the maximum allowed. The invention can be used with regulators subject to design requirements that specify a minimum time T. sub. min between load transients, and with those for which no T. sub. min is specified.

US Patent:

20190181746, Jun 13, 2019

Filed:

Feb 14, 2019

Appl. No.:

16/276269

Inventors:

- Phoenix AZ, US
Gabor REIZIK - Dublin CA, US

Assignee:

SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC - Phoenix AZ

International Classification:

H02M 1/15
H02M 3/158
H02M 3/156
H03K 7/08

Abstract:

A controller controls Pulse Width Modulation (PWM) signals of one or more phases. The controller includes a phase sequencer to select a phase, a common ramp generator generating a common ramp signal, a phase activation circuit to turn on the PWM signal of the selected phase based on the common ramp signal, and for each phase a Current Sense plus Ramp (CSR) signal generator to generate a phase CSR signal according to a current of the phase and a phase deactivation circuit to turn off the PWM signal of the phase based on the phase CSR signal. A method of controlling PWM phases comprises selecting a phase, generating a common ramp signal, turning on the PWM signal of the selected phase based on the common ramp signal, generating CSR signals according to currents of the phases, and turning off the PWM signals based on the respective CSR signals.