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Friedrich J Taenzler

from Plano, TX

Friedrich Taenzler Phones & Addresses

  • 2508 Suntree Ln, Plano, TX 75025 • 972 491-9030
  • 2508 Suntree Ln, Plano, TX 75025 • 972 800-6099

Work

  • Company:
    Texas instruments
    1995
  • Position:
    Pde manager

Skills

Mixed Signal • Semiconductors • Analog • Ic • Soc • Product Engineering • Semiconductor Industry • Cmos • Testing • Asic • Electronics • Test Engineering • Debugging • Rf • Test Equipment • Power Management • Dft • Analog Circuit Design • Fpga • Silicon • Simulations • Electrical Engineering • Characterization • Yield • Bist • Serdes

Emails

Industries

Semiconductors

Resumes

Friedrich Taenzler Photo 1

Pde Manager

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Location:
Dallas, TX
Industry:
Semiconductors
Work:
Texas Instruments
Pde Manager

Texas Instruments
Rf-Engineering Manager
Skills:
Mixed Signal
Semiconductors
Analog
Ic
Soc
Product Engineering
Semiconductor Industry
Cmos
Testing
Asic
Electronics
Test Engineering
Debugging
Rf
Test Equipment
Power Management
Dft
Analog Circuit Design
Fpga
Silicon
Simulations
Electrical Engineering
Characterization
Yield
Bist
Serdes

Us Patents

  • Apparatus And Method For Evaluating The Performance Of Systems Having Time-Varying Output Characteristics

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  • US Patent:
    20100082278, Apr 1, 2010
  • Filed:
    Sep 30, 2008
  • Appl. No.:
    12/241479
  • Inventors:
    Ganesh Parasuram Srinivasan - Richardson TX, US
    Friedrich Johannes Taenzler - Plano TX, US
  • International Classification:
    G06F 19/00
    G06F 15/00
  • US Classification:
    702 82, 702189
  • Abstract:
    An apparatus for evaluating a system. The apparatus can include a storage element for receiving at least one time-varying output characteristic of the system, the time-varying output characteristic comprising a plurality of raw data points representing a plurality of measurements at a plurality of times; and a processing element communicatively coupled to the storage element. The processing element can be configured for partitioning the plurality of raw data points into a plurality of segments, calculating a plurality of estimated data points based on a plurality of mathematical expressions, and characterizing the system based on at least one figure of merit (FOM) computed from the plurality of estimated data points. In the apparatus, at least one of the plurality of mathematical expressions is associated with each of the plurality of segments.
  • Multi-Frame Test Signals Modulated By Digital Signal Comprising Source For Testing Analog Integrated Circuits

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  • US Patent:
    20100228515, Sep 9, 2010
  • Filed:
    Mar 6, 2009
  • Appl. No.:
    12/399687
  • Inventors:
    GANESH P. SRINIVASAN - DALLAS TX, US
    FRIEDRICH J. TAENZLER - PLANO TX, US
  • Assignee:
    TEXAS INSTRUMENTS INC - DALLAS TX
  • International Classification:
    G01R 31/00
    G06F 19/00
  • US Classification:
    702124, 324537
  • Abstract:
    A method of generating multi-frame test signals, a testing apparatus, and method for testing integrated circuits (ICs) with the multi-frame test signals. An analog source generates an analog source signal at a constant power and a constant frequency that is modulated with a first modulating signal (e.g., I) to output a first test signal having first signal parameters including a power level, a frequency and a modulation scheme. The modulating is repeated with a second modulating signal (e.g., Q) to output a second test signal having second signal parameters including a power level, a frequency and a modulation scheme. At least one of the first and second signal parameters are different. The modulating signals are generated by a digital signal source. The first and second test signal are combined by placing the first test signal on the first frame (frame ) and the second test signal on the second frame (frame ) of the multi-frame test signal.
  • Method And System For Testing An Electric Circuit

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  • US Patent:
    20120169359, Jul 5, 2012
  • Filed:
    Dec 29, 2010
  • Appl. No.:
    12/980638
  • Inventors:
    Bruce C. Kim - Tuscaloosa AL, US
    Ganesh Srinivasan - Dallas TX, US
    Friedrich Taenzler - Plano TX, US
  • Assignee:
    The Board of Trustees of the University of Alabama for and on behalf of the University of Alabama - Tuscaloosa AL
  • International Classification:
    G01R 31/28
  • US Classification:
    32475001
  • Abstract:
    Embodiments include a method and system for testing an electric circuit. A carrier signal of a first frequency is modulated with a multi-tone signal to generate a test signal. The test signal is applied to an input of a circuit under test (CUT). A crest factor of an output signal that corresponds to the test signal received at an output of the CUT is measured. A crest factor differential between the measured crest factor and a reference crest factor is determined. If the crest factor differential exceeds a threshold value, the CUT is determined to be defective.

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