Frederick A Ziegler

US Patent:

6337584, Jan 8, 2002

Filed:

Aug 25, 1999

Appl. No.:

09/382760

Inventors:

Andrew Douglas Davies - Rochester MN
Daniel Lawrence Stasiak - Rochester MN
Frederick Jacob Ziegler - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 1920

US Classification:

326121, 326 98, 326 95, 326290

Abstract:

A method and apparatus for reducing bipolar current effects in dynamic logic circuits that are fabricated using the SOI technology is disclosed. A dynamic logic circuit capable of reducing bipolar current effects includes a precharge transistor (or a discharge transistor), a pass transistor, a functional logic circuit block, and an inverter. Connected in series with the precharge transistor, the functional logic circuit block, which includes multiple transistors, receives signal inputs. The pass transistor, connected in parallel with the precharge transistor, receives an identical input as one of the many transistors within the functional logic circuit block. The inverter, connected to a node between the precharge transistor and the functional logic circuit block, provides an output for the dynamic logic circuit.

US Patent:

7065101, Jun 20, 2006

Filed:

Nov 15, 2001

Appl. No.:

10/003366

Inventors:

Frederick J. Ziegler - Rochester MN, US
Mark J. Hickey - Rochester MN, US
Jack C. Randolph - Rochester MN, US
Susan M. Cox - Rochester MN, US
Dale J. Thomforde - Pine Island MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04J 3/22
H04J 3/06

US Classification:

370467, 370503, 370535, 375354, 710 71

Abstract:

An apparatus for enabling transmission of parallel data from a first parallel bus to a second parallel bus via a serial data channel includes a first logic element that generates a synchronization character used in a serial data transmission protocol upon detection of a parallel synchronization packet. A serializer converts data from the first logic element into a serial data stream. A de-serializer converts the serial data stream into a plurality of parallel data packets. A second logic element detects the synchronization character and converts the synchronization character into a parallel synchronization packet.

US Patent:

7079528, Jul 18, 2006

Filed:

Dec 13, 2001

Appl. No.:

10/022020

Inventors:

Frederick J. Ziegler - Rochester MN, US
Mark J. Hickey - Rochester MN, US
Jack C. Randolph - Rochester MN, US
Susan M. Cox - Rochester MN, US
Dale J. Thomforde - Pine Island MN, US
Robert N. Newshutz - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/66

US Classification:

370352, 370365, 370366, 370535, 370539, 341100, 341101

Abstract:

In a method of communicating a plurality of parallel data packets from a first data parallel bus to a second parallel data bus, each of the plurality of parallel data packets is separated into a first portion and a second portion. Each first portion is converted into a first serial data stream and each second portion is converted into a second serial data stream. The first serial data stream is transmitted over a first serial data channel and the second serial data stream is transmitted over a second serial data channel. The first serial data stream is converted into a plurality of first received portions and the second serial data stream is converted into a plurality of second received portions. Selected first received portions are combined with corresponding selected second received portions so as to regenerate the plurality of parallel data packets.

US Patent:

7187863, Mar 6, 2007

Filed:

Dec 13, 2001

Appl. No.:

10/021961

Inventors:

Susan Marie Cox - Rochester MN, US
Mark Joseph Hickey - Rochester MN, US
Jack Chris Randolph - Rochester MN, US
Dale John Thomforde - Pine Island MN, US
Frederick Jacob Ziegler - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04J 14/00

US Classification:

398 43, 370536, 385 24

Abstract:

In a first aspect, a stream of data is transmitted by dividing the stream of data into a first substream and a second substream, transmitting the first substream in a first data channel, and transmitting the second substream in a second data channel. Before transmitting the first and second substreams, a first marker signal is inserted in the first substream and/or a second marker signal is inserted in the second substream. A receiver circuit receives the substreams, detects at least one marker signal, and reassembles the data stream from the substreams based on at least one detected marker signal. Numerous other aspects are provided.

US Patent:

8495643, Jul 23, 2013

Filed:

Jun 30, 2009

Appl. No.:

12/494541

Inventors:

Mark Gary Kupferschmidt - Rochester MN, US
Eric Oliver Mejdrich - Rochester MN, US
Paul Emery Schardt - Rochester MN, US
Frederick Jacob Ziegler - Pine Island MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/46
G06F 9/30

US Classification:

718103, 712205

Abstract:

A method and circuit arrangement process a workload in a multithreaded processor that includes a plurality of hardware threads. Each thread receives at least one message carrying data to process the workload through a respective inbox from among a plurality of inboxes. A plurality of messages are received at a first inbox among the plurality of inboxes, wherein the first inbox is associated with a first thread among the plurality of hardware threads, and wherein each message is associated with a priority. From the plurality of received messages, a first message is selected to process in the first thread based on that first message being associated with the highest priority among the received messages. A second message is selected to process in the first thread based on that second message being associated with the earliest time stamp among the received messages and in response to processing the first message.

US Patent:

20030112827, Jun 19, 2003

Filed:

Dec 13, 2001

Appl. No.:

10/022139

Inventors:

Susan Cox - Rochester MN, US
Mark Hickey - Rochester MN, US
Jack Randolph - Rochester MN, US
Dale Thomforde - Pine Island MN, US
Frederick Ziegler - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04J003/06

US Classification:

370/509000, 370/512000

Abstract:

A method of deskewing parallel data streams includes receiving the plurality of data streams and storing each of the received data streams in a respective buffer. Synchronization signals in the data streams are detected, and the buffers are controlled to read out the stored data streams on the basis of the detected synchronization signals. Numerous other methods and apparatus are provided.

US Patent:

56048823, Feb 18, 1997

Filed:

Aug 27, 1993

Appl. No.:

8/113554

Inventors:

Russell D. Hoover - Rochester MN
John C. Willis - Rochester MN
Donald F. Baldus - Mazeppa MN
Frederick J. Ziegler - Rochester MN
Lishing Liu - Pleasantville NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1208

US Classification:

395448

Abstract:

A multiprocessor in which processing units have local private caches and records are stored on at least a first global storage control unit. An interconnection system provides node to node data and synchronization communications between processing units and the first global storage control unit. The global storage control unit includes a coherency controller for tracking each instance of records owned by the global storage control unit currently resident on the processing units. Each processing unit executes a cache management process for freeing intervals of the local cache for the processing unit. Upon identification of an interval, the processing unit sends empty notification to the global storage control unit owning the record an instance of which was resident in the interval. Thereafter the interval is marked as invalid in a cache directory for the processing unit and indicia for the instance is deleted from a coherency directory for the global storage control unit.

US Patent:

57617210, Jun 2, 1998

Filed:

Jul 11, 1996

Appl. No.:

8/678336

Inventors:

Donald Francis Baldus - Mazeppa MN
Nancy Joan Duffield - Rochester MN
Russell Dean Hoover - Rochester MN
John Christopher Willis - Rochester MN
Frederick Jacob Ziegler - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711141

Abstract:

A method and system for providing cache coherence despite unordered interconnect transport. In a computer system of multiple memory devices or memory units having shared memory and an interconnect characterized by unordered transport, the method comprises sending a request packet over the interconnect from a first memory device to a second memory device requiring that an action be carried out on shared memory held by the second memory device. If the second memory device determines that the shared memory is in a transient state, the second memory device returns the request packet to the first memory device; otherwise, the request is carried out by the second memory device. The first memory device will continue to resend the request packet each time that the request packet is returned.

Author:

Frederick J. Ziegler

ISBN #:

0842270973