Fred A Weber

US Patent:

6397239, May 28, 2002

Filed:

Feb 6, 2001

Appl. No.:

09/778352

Inventors:

Stuart F. Oberman - Sunnyvale CA
Norbert Juffa - San Jose CA
Fred Weber - San Jose CA
Krishnan Ramani - Sunnyvale CA
Ravi Krishna Cherukuri - Milpitas CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 742

US Classification:

708505, 708495

Abstract:

A multimedia execution unit configured to perform vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far path is configured to handle effective addition operations and effective subtraction operations for operands having an absolute exponent difference greater than one. The close path is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close path is configured to generate two output values, wherein one output value is the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. Selection of the first or second output value in the close path effectuates the round-to-nearest operation for the output of the adder.

US Patent:

61345741, Oct 17, 2000

Filed:

May 8, 1998

Appl. No.:

9/075073

Inventors:

Stuart F. Oberman - Sunnyvale CA
Norbert Juffa - San Jose CA
Fred Weber - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 752
G06F 7552

US Classification:

708551

Abstract:

A multiplier configured to obtain higher frequencies of exactly rounded results by adding an adjustment constant to intermediate products generated during iterative multiplication operations is disclosed. One such iterative multiplication operation is the Newton-Raphson iteration, which may be utilized by the multiplier to perform reciprocal calculations and reciprocal square root calculations. For each iteration, the results converge toward an infinitely precise result. To improve the frequency of the exactly rounded result, the results of the iterative calculations may be studied for a large number of differing input operands to determine the best suited value for the adjustment constant. The multiplier may also be configured to perform scalar and packed vector multiplication using the same hardware.

US Patent:

61157325, Sep 5, 2000

Filed:

May 8, 1998

Appl. No.:

9/075418

Inventors:

Stuart F. Oberman - Sunnyvale CA
Norbert Juffa - San Jose CA
Fred Weber - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 752

US Classification:

708625

Abstract:

A processor capable of efficiently performing iterative calculations is disclosed. The processor comprises a multiplier that is configured to perform iterative multiplication operations to evaluate constant powers of an operand such as the reciprocal and reciprocal square root. Intermediate products that are formed are compressed and decompressed to reduce interim storage requirements. The intermediate products may be rounded and normalized in two paths, one assuming an overflow will occur, and then compressed and stored for use in the next iteration.

US Patent:

61157333, Sep 5, 2000

Filed:

May 8, 1998

Appl. No.:

9/074826

Inventors:

Stuart F. Oberman - Sunnyvale CA
Norbert Juffa - San Jose CA
Fred Weber - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 7552

US Classification:

708654

Abstract:

A processor capable of efficiently evaluating constant powers of an operand such as the reciprocal and reciprocal square root is disclosed. The processor comprises a multiplier that is configured to perform iterative multiplication operations to evaluate constant powers of an operand such as the reciprocal and reciprocal square root. Intermediate products that are formed may be rounded and normalized in two paths, one assuming an overflow will occur, and then compressed and stored for use in the next iteration. The processor comprises a multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier may performing rounded by adding a rounding constant.

US Patent:

62983679, Oct 2, 2001

Filed:

Apr 6, 1998

Appl. No.:

9/055916

Inventors:

Stuart F. Oberman - Sunnyvale CA
Norbert Juffa - San Jose CA
Fred Weber - San Jose CA
Krishnan Ramani - Sunnyvale CA
Ravi Krishna - Milpitas CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 738

US Classification:

708524

Abstract:

A multimedia execution unit configured to perform vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far path is configured to handle effective addition operations and effective subtraction operations for operands having an absolute exponent difference greater than one. The close path is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close path is configured to generate two output values, wherein one output value is the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. Selection of the first or second output value in the close path effectuates the round-to-nearest operation for the output of the adder. The execution unit may be configured to perform vectored addition and subtraction, integer/floating point conversion, reverse subtraction, accumulate, extreme value (minimum/maximum), and comparison instructions.

US Patent:

20170139823, May 18, 2017

Filed:

Nov 20, 2015

Appl. No.:

14/947931

Inventors:

- Gyeonggi-DO, KR
Fred WEBER - San Jose CA, US

International Classification:

G06F 12/02
G06F 11/20
G06F 12/10
H04L 29/08
G06F 3/06

Abstract:

In one embodiment, a distributed storage system comprises: a plurality of appliances, a distributed multimode storage management coordinator, and a communication mechanism for communicating distributed multimode storage management messages. A first one of the plurality of appliances can include: a plurality of storage devices that have a first storage partition including a first type of interface and a first information storage region and a second storage partition including a selective underlying exposure (SUE) interface and a second information storage region that stores a second type of information, wherein the SUE interface exposes an aspect of the second information storage region. The distributed multimode storage management coordinator can include a plurality of multimode storage management systems that direct conveyance of information to the plurality of storage devices, wherein the coordinator includes a multiple mode SUE management system that directs file activities of the second partitions via the SUE interface.

Author:

Fred Weber

ISBN #:

0711974799

Author:

Fred Weber

ISBN #:

0711974845

Author:

Fred Weber

ISBN #:

0711974853

Author:

Fred Weber

ISBN #:

0711975299

Author:

Fred Weber

ISBN #:

0757900267

Author:

Fred Weber

ISBN #:

0757900275

Author:

Fred Weber

ISBN #:

0757900305

Author:

Fred Weber

ISBN #:

0757902162