Frank J Baker

Author:

Frank J. Baker

ISBN #:

0801630576

Author:

Frank J. Baker

ISBN #:

0809270420

Author:

Frank J. Baker

ISBN #:

0809270439

Author:

Frank J. Baker

ISBN #:

0879492082

Author:

Frank B. Baker

ISBN #:

0435080032

Author:

Frank B. Baker

ISBN #:

0435080040

Author:

Frank B. Baker

ISBN #:

0435080059

Author:

Frank B. Baker

ISBN #:

0435080199

US Patent:

57125015, Jan 27, 1998

Filed:

Oct 10, 1995

Appl. No.:

8/541536

Inventors:

Robert B. Davies - Tempe AZ
Frank K. Baker - Austin TX
Jon J. Candelaria - Tempe AZ
Andreas A. Wild - Scottsdale AZ
Peter J. Zdebel - Mesa AZ

Assignee:

Motorola, Inc. - Shaumburg IL

International Classification:

H01L 2976
H01L 2994

US Classification:

257335

Abstract:

A graded-channel semiconductor device (10) includes a substrate region (11) having a major surface (12). A source region (13) and a drain region (14) are formed in the substrate region (11) and are spaced apart to form a channel region (16). A doped region (18) is formed in the channel region (16) and is spaced apart from the source region (13), the drain region (14), and the major surface (12). The doped region (18) has the same conductivity type as the channel region (16), but has a higher dopant concentration. The device (10) exhibits an enhanced punch-through resistance and improved performance compared to prior art short channel structures.

US Patent:

56610483, Aug 26, 1997

Filed:

Mar 21, 1995

Appl. No.:

8/408654

Inventors:

Robert B. Davies - Tempe AZ
Chandrasekhara Sudhama - Scottsdale AZ
Frank K. Baker - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 21265

US Classification:

438217

Abstract:

An insulated gate field effect transistor (10) having a reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor substrate (11) and a drain extension region (25) is formed in the dopant well (13). An oxide layer (26) is formed on the dopant well (13) wherein the oxide layer (26) has a thickness of at least 400 angstroms. A gate structure (61) having a gate shunt portion (32) over a thinned portion of the oxide (26) and a gate extension portion (58) over an unthinned portion of the oxide (26). The thinned portion of the oxide (26) forms a gate oxide of the field effect transistor (10) and the unthinned portion lowers a capacitance of the gate shunt portion (32) of the field effect transistor (10).

US Patent:

55411320, Jul 30, 1996

Filed:

Mar 21, 1995

Appl. No.:

8/408653

Inventors:

Robert B. Davies - Tempe AZ
Vida Ilderem - Phoenix AZ
Mark D. Griswold - Chandler AZ
Diann Dow - Chandler AZ
James E. Prendergast - Phoenix AZ
Iksung Lim - Tempe AZ
Juan Buxo - Mesa AZ
Richard D. Sivan - Austin TX
James D. Burnett - Austin TX
Frank K. Baker - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 21265

US Classification:

437 45

Abstract:

An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor material (11). A gate oxide layer (26) is formed on the dopant well (13) wherein the gate oxide layer (26) and a gate structure (41) having a gate contact portion (43) and a gate extension portion (44). The gate contact portion (43) permits electrical contact to the gate structure (41), whereas the gate extension portion (44) serves as the active gate portion. A portion of the gate oxide (26) adjacent the gate contact portion (43) is thickened to lower a gate to drain capacitance of the field effect transistor (10) and thereby increase a bandwidth of the insulated gate field effect transistor (10).

US Patent:

48015555, Jan 31, 1989

Filed:

Jan 14, 1987

Appl. No.:

7/003176

Inventors:

Patrick J. Holly - Tempe AZ
Louis C. Parrillo - Austin TX
Frank K. Baker - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 0000

US Classification:

437 29

Abstract:

A process for forming graded source/drain regions in semiconductor devices involves two ion implantation steps and an optional drive-in step. The first implantation is a low dose implant with high energy and/or low mass ions to form the deeper grading region. The second implant is a high does implant with low energy and/or high mass ions to form the shallower, lower resistivity source/drain region. Without the optional drive-in step, virtually no lateral grading takes place, resulting in little encroachment of the grading region under the gate. The use of a drive-in step between the two implant steps causes diffusion of the grading dopant, which increases the grading both laterally and vertically, resulting in better breakdown and capacitance characteristics, but increased encroachment under the gate. The present invention allows control over the lateral and vertical grading separately to optimize the trade-offs for a particular application.