Frank Eugene Baker

US Patent:

6444545, Sep 3, 2002

Filed:

Dec 19, 2000

Appl. No.:

09/740249

Inventors:

Michael A. Sadd - Austin TX
Sucharita Madhukar - Austin TX
Frank Kelsey Baker - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2120

US Classification:

438503, 438257

Abstract:

A semiconductor device structure for storing charge has a silicon nitride layer, in which a plurality of nanoclusters are sandwiched between oxide layers. The nanoclusters and the silicon nitride make up a storage region, which is particularly useful in non-volatile memories. The nanoclusters provide a repository for holes or electrons that jump from trap to trap in the silicon nitride when the silicon nitride is heated. This results in much of the charge, which would normally leak off from the silicon nitride at high temperatures, remaining in the storage region due to trapping in the nanoclusters. The silicon nitride layer with nanoclusters therein is formed by depositing a silicon nitride layer, then nanoclusters, and then another silicon nitride layer or by depositing a silicon-rich silicon nitride layer and subsequent heating to cause it to transform to a regular silicon nitride layer with silicon nanoclusters therein.

US Patent:

6812517, Nov 2, 2004

Filed:

Aug 29, 2002

Appl. No.:

10/230810

Inventors:

Frank Kelsey Baker - Austin TX

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 29788

US Classification:

257315, 257E29309

Abstract:

A non-volatile memory (NVM) cell, which uses a storage dielectric as the storage element, has a top dielectric between a gate and the storage dielectric and a bottom dielectric between a semiconductor substrate and the storage dielectric. The top dielectric includes a relatively thick and high k dielectric layer and an interfacial layer. The interfacial layer is very thin and has a higher k than silicon oxide. The bottom dielectric layer is preferably silicon oxide because of its interfacial and tunneling properties. The cell thus has benefits resulting from a well-passivated, high k top dielectric in combination with a bottom dielectric of silicon oxide.

US Patent:

7135370, Nov 14, 2006

Filed:

Jul 1, 2004

Appl. No.:

10/883237

Inventors:

Frank Kelsey Baker - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/336

US Classification:

438257, 438261, 438288, 438770, 438785

Abstract:

A non-volatile memory (NVM) cell, which uses a storage dielectric as the storage element, has a top dielectric between a gate and the storage dielectric and a bottom dielectric between a semiconductor substrate and the storage dielectric. The top dielectric includes a relatively thick and high k dielectric layer and an interfacial layer. The interfacial layer is very thin and has a higher k than silicon oxide. The bottom dielectric layer is preferably silicon oxide because of its interfacial and tunneling properties. The cell thus has benefits resulting from a well-passivated, high k top dielectric in combination with a bottom dielectric of silicon oxide.

US Patent:

20020103959, Aug 1, 2002

Filed:

Jan 30, 2001

Appl. No.:

09/772830

Inventors:

Frank Baker - Austin TX, US
James Burnett - Austin TX, US
Thomas Jew - Austin TX, US

International Classification:

G06F012/00

US Classification:

711/103000, 711/001000

Abstract:

A memory system () has an array of addressable storage elements () arranged in a plurality of rows and a plurality of columns, and decoding circuitry () coupled to the array of addressable storage elements (). The decoding circuitry (), in response to decoding a first address, accesses a first storage element of a first row of the plurality of rows, and, in response to decoding a second address consecutive to the first address, accesses a second storage element of a second row of the plurality of rows. The second row of the plurality of rows is different from the first row of the plurality of rows. By implementing a memory system wherein consecutive addresses correspond to storage elements of different rows, read disturb stresses along a single row can be minimized.

US Patent:

20030113962, Jun 19, 2003

Filed:

Dec 14, 2001

Appl. No.:

10/017427

Inventors:

Gowrishankar Chindalore - Austin TX, US
Frank Baker - Austin TX, US
Paul Ingersoll - Austin TX, US
Alexander Hoefler - Austin TX, US

International Classification:

H01L021/8238

US Classification:

438/201000

Abstract:

A semiconductor device () comprises an underlying insulating layer (), an overlying insulating layer () and a charge storage layer () between the insulating layers (). The charge storage layer () and the overlying insulating layer () form an interface, where at least a majority of charge in the charge storage layer () is stored. This can be accomplished by forming a charge storage layer () with different materials such as silicon and silicon germanium layers or n-type and p-type material layers, in one embodiment. In another embodiment, the charge storage layer () comprises a dopant that is graded. By storing at least a majority of the charge at the interface between the charge storage layer () and the overlying insulating layer (), the leakage of charge through the underlying insulating layer is decreased allowing for a thinner underlying insulating layer () to be used.

US Patent:

20040084710, May 6, 2004

Filed:

Oct 30, 2002

Appl. No.:

10/283748

Inventors:

Frank Baker - Austin TX, US
Alexander Hoefler - Austin TX, US
Erwin Prinz - Austin TX, US

International Classification:

H01L027/108

US Classification:

257/311000

Abstract:

A semiconductor nonvolatile memory cell () comprising a split-gate FET device having a charge-storage transistor () in series with a select transistor (). A multilayered charge-storage gate dielectric () extends over at least a portion of the source () and a first portion () of the channel of the FET. A select gate dielectric (), contiguous to the charge-storage gate dielectric, extends over at least a portion of the drain () and a second portion () of the channel. A monolithic gate conductor () overlies both the charge-storage gate dielectric and the select gate dielectric. In an embodiment, the charge-storage gate dielectric is an ONO stack that incorporates a thin-film nitride charge-storage layer (). The select transistor operates to inhibit over-erasure of the NVM cell. The thin-film nitride charge-storage layer extends laterally over a substantial portion of the channel so as to enhance data retention by the cell.

US Patent:

20040085815, May 6, 2004

Filed:

Nov 4, 2002

Appl. No.:

10/287328

Inventors:

Erwin Prinz - Austin TX, US
Craig Swift - Austin TX, US
Jane Yater - Austin TX, US
Frank Baker - Austin TX, US

International Classification:

G11C016/04

US Classification:

365/185180

Abstract:

A technique for reducing the read gate voltage in a memory array including memory cells having a transistor for storing charge indicative of the value stored in the cell. In one example, a voltage greater than the substrate voltage is applied to the sources of the transistors of the memory cells of the array to increase the threshold voltage of a transistor due the body effect. The read gate voltage is greater than the source voltage which is greater than the substrate voltage. A non read voltage of less than the source voltage is applied to the gates of the transistors of the unselected rows to reduce leakage current. With this embodiment, the threshold voltages of transistors having an erased state can be less than 0V. With some embodiments, the read disturb caused by a gate voltage can be reduced due to the reduction in the gate voltage. In other examples, a negative voltage is applied to the gates of unselected rows to prevent leakage current. Accordingly, the voltage thresholds of transistors having an erased state can be reduced, wherein the read gate voltage can be reduced as well.

US Patent:

20040159881, Aug 19, 2004

Filed:

Feb 13, 2004

Appl. No.:

10/779004

Inventors:

Gowrishankar Chindalore - Austin TX, US
Frank Baker - Austin TX, US
Paul Ingersoll - Austin TX, US
Alexander Hoefler - Austin TX, US

International Classification:

H01L021/8238
H01L029/788

US Classification:

257/324000, 438/216000, 257/321000, 438/263000

Abstract:

A semiconductor device () comprises an underlying insulating layer (), an overlying insulating layer () and a charge storage layer () between the insulating layers (). The charge storage layer () and the overlying insulating layer () form an interface, where at least a majority of charge in the charge storage layer () is stored. This can be accomplished by forming a charge storage layer () with different materials such as silicon and silicon germanium layers or n-type and p-type material layers, in one embodiment. In another embodiment, the charge storage layer () comprises a dopant that is graded. By storing at least a majority of the charge at the interface between the charge storage layer () and the overlying insulating layer (), the leakage of charge through the underlying insulating layer is decreased allowing for a thinner underlying insulating layer () to be used.

Address:

1800 Casa Sierra, Canyon Lake, TX 78133

Phone:

830 964-4976

VIN:

3VWEF71K17M142357

Make:

VOLKSWAGEN

Model:

JETTA

Year:

2007

Author:

Frank J. Baker

ISBN #:

0801630576

Author:

Frank J. Baker

ISBN #:

0809270420

Author:

Frank J. Baker

ISBN #:

0809270439

Author:

Frank J. Baker

ISBN #:

0879492082

Author:

Frank B. Baker

ISBN #:

0435080032

Author:

Frank B. Baker

ISBN #:

0435080040

Author:

Frank B. Baker

ISBN #:

0435080059

Author:

Frank B. Baker

ISBN #:

0435080199