Franco Karyn Ricci

Author:

Franco Carlo Ricci

ISBN #:

8849507844

Author:

Franco Ricci

ISBN #:

0802035078

Author:

Franco Ricci

ISBN #:

0919473717

Author:

Franco Ricci

ISBN #:

0889209901

US Patent:

6639827, Oct 28, 2003

Filed:

Mar 12, 2002

Appl. No.:

10/097202

Inventors:

Lawrence T. Clark - Phoenix AZ
Franco Ricci - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 1100

US Classification:

365154, 365227, 36522306, 36518911

Abstract:

An integrated circuit having CMOS transistors processed with different gate-oxide thicknesses. The transistors having the thinner gate-oxide may be used to generate data values that may be stored by the transistors having the thicker gate-oxides. The thicker gate-oxides may reduce gate leakage currents during a system standby mode.

US Patent:

6774696, Aug 10, 2004

Filed:

Dec 12, 2002

Appl. No.:

10/318689

Inventors:

Lawrence T. Clark - Phoenix AZ
Shay P. Demmons - Chandler AZ
Franco Ricci - Chandler AZ
Tim Beatty - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03L 500

US Classification:

327333

Abstract:

A level translator block receives a control signal and a data signal and provides an interface between circuitry operating in a first voltage domain and circuitry operating in a second voltage domain. Thick-oxide transistors are appropriately used in the level translator block to reduce gate leakage currents when translating signals.

US Patent:

6775180, Aug 10, 2004

Filed:

Dec 23, 2002

Appl. No.:

10/329124

Inventors:

Manish Biyani - Chandler AZ
Lawrence T. Clark - Phoenix AZ
Shay P. Demmons - Chandler AZ
Franco Ricci - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 1100

US Classification:

365154, 365156, 36518905

Abstract:

An integrated circuit having a state retentive memory structure to store state values. A high performance section uses thin gate-oxide transistors and the state retentive memory structure uses thick gate-oxide transistors to capture and retain the state values when operating in a low power mode.

US Patent:

7200060, Apr 3, 2007

Filed:

Jul 15, 2003

Appl. No.:

10/620469

Inventors:

Timothy S. Beatty - Mesa AZ, US
Franco Ricci - Chandler AZ, US
Lawrence T. Clark - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 7/00

US Classification:

365203, 36518905, 36518908

Abstract:

A memory driver architecture and associated methods are generally described.

US Patent:

7796445, Sep 14, 2010

Filed:

Feb 12, 2008

Appl. No.:

12/029908

Inventors:

Manish Biyani - Chandler AZ, US
Franco Ricci - Chandler AZ, US

Assignee:

Marvell International, Ltd. - Hamilton

International Classification:

G11C 7/00

US Classification:

36518905, 36518508, 365154

Abstract:

A device can include 1) a sustained or constantly powered low leakage latch to and from which a volatile state is uploaded and downloaded, respectively, based on an active-to-low signal, and 2) an intermittently powered or de-powerable memory element, coupled to the low leakage latch, from which and to which the volatile state is uploaded and downloaded, respectively, based on the active-to-low signal and a de-powerable voltage across the de-powerable memory element is powered and un-powered, respectively.

US Patent:

8607090, Dec 10, 2013

Filed:

Feb 28, 2011

Appl. No.:

13/036287

Inventors:

Kim Schuttenberg - Gilbert AZ, US
Franco Ricci - Chandler AZ, US

Assignee:

Marvell International Ltd.

International Classification:

G06F 1/04

US Classification:

713503

Abstract:

Systems, methods, and other embodiments associated with selective shorting are described. According to one embodiment, an apparatus includes a selective shorting device connected between clock branches. The selective shorting device is configured to selectively electrically connect the clock branches to one another and to selectively electrically disconnect the clock branches from one another. The apparatus also includes a selective shorting control mechanism that controls the selective shorting device to electrically connect the clock branches during a controlling portion of a clock signal. The selective shorting control mechanism is configured to electrically disconnect the clock branches in the absence of the controlling portion.

US Patent:

20040128574, Jul 1, 2004

Filed:

Dec 31, 2002

Appl. No.:

10/335960

Inventors:

Franco Ricci - Chandler AZ, US
Shay Demmons - Chandler AZ, US
Lawrence Clark - Phoenix AZ, US
Timothy Beatty - Mesa AZ, US
Michael Wilkerson - Mesa AZ, US
Byungwoo Choi - Chandler AZ, US

International Classification:

G06F001/32

US Classification:

713/320000

Abstract:

Techniques and apparatuses for reducing power consumption in processor based systems during active and standby modes. A low power TLB is disclosed that does not precharge invalid entries or write to output circuits physical addresses that are the same as immediately preceding lookups. A circuit to acknowledge that the integrated circuits of the processor have entered low power standby mode that is low leakage and consumes little power is disclosed. Minimum delay buffers that have very low leakage because of series placement of a long delay enable transistor with the transistors of the inverters that make up the buffers is also disclosed.

US Patent:

59097027, Jun 1, 1999

Filed:

Sep 30, 1996

Appl. No.:

8/724610

Inventors:

Marc Jalfon - Haifa, IL
David Regenold - Mesa AZ
Franco Ricci - Chandler AZ
Ramprasad Satagopan - Sunnyvale CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

711203

Abstract:

A multiprocessor data processing system includes a private data bus and a private program bus coupled to each of the processors. Coupled between the private data buses is a plurality of memory banks, each of which can be dynamically switched between the processors to move blocks of data without physically transferring the data from one bank to another. Likewise, a plurality of memory banks is coupled between the program buses. These memory banks are loaded with pages of program instructions from external memory over a shared bus. Any one of the pages can be coupled to either of the processors on its respective private program bus. When the pages are coupled to the shared bus, they appear as a contiguous address space. When a page is coupled to one of the private program buses, the addressing mode is changed so that the page is mapped to a common address space. This permits the program code to be loaded into any available page, and the processors can execute the code regardless of where it has been loaded, thereby permitting easy relocatability.