Fong E Luk from 1065 Broadmoor Blvd, San Leandro, CA 94577, age 75, Phone: 510 864-4088

High Speed Electromechanically Driven Test Ahead
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US Patent:

7235993, Jun 26, 2007
Filed:

Jul 8, 2004
Appl. No.:

10/887965
Inventors:

Fong Luk - Alameda CA, US
International Classification:

G01R 31/02
US Classification:

324761
Abstract:

A method for testing an integrated circuit (IC) that includes a step of mechanically turning on off an electrical connection to a test pin disposed on an electronic test head. The method further includes a step of rotating a driving rod to engage a switching wheel or other similar means for turning on-off of an electrical connection.

Generation Of Test Vectors For Testing Electronic Circuits Taking Into Account Of Defect Probability
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US Patent:

7266741, Sep 4, 2007
Filed:

Nov 19, 2004
Appl. No.:

10/992922
Inventors:

Fong Luk - Alameda CA, US
International Classification:

G01R 31/28
US Classification:

714724, 714738
Abstract:

A method for generating test pattern signals weighted by the fault probability to greatly simplify the test process and to reduce the number of test vectors required for conducting the integrated circuit functionality tests. The method takes into consideration that the electrical short conditions occur mostly between adjacent nodes. The “fault coverage” concept is revised to test faults occurred between adjacent nodes and the test vectors are generated based a fault-probability weighted algorithm such that tests are conducted mostly on connections between adjacent nodes either on a same horizontal layer of between vertical nodes having vertical overlapping areas.

Simplified High Speed Test System
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US Patent:

7409620, Aug 5, 2008
Filed:

Nov 29, 2005
Appl. No.:

11/290373
Inventors:

Fong Luk - Alameda CA, US
International Classification:

G01R 31/28
G06F 11/00
US Classification:

714742, 714701, 714703, 714738
Abstract:

A method for configuring a testing system that includes a step of connecting a commercially available computer (CACMP) for directly controlling transmission of a plurality of test vectors to a test head. The method further includes a step of connecting a test vector memory between the CACMP and the formatter unit (FTM) with response unit (RP) for providing a required data width for storing the test vectors therein.

Control Adjustable Device Configurations To Induce Parameter Variations To Control Parameter Skews
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US Patent:

7487571, Feb 10, 2009
Filed:

Nov 29, 2005
Appl. No.:

11/290714
Inventors:

Fong Luk - Alameda CA, US
International Classification:

G06F 17/50
US Classification:

16 4, 716 5, 716 6, 716 16, 714724, 714725, 714726, 324763, 324764, 324765
Abstract:

A method is used for configuring an electronic device to reduce a skew of a parameter. The method includes a step of incorporating a plurality of controllable built-in parameter variation adjusting circuits for effecting a small step-change in the parameter at different points of the electronic device for reducing said skew of the parameter. A specific example of the method is to incorporate one or a plurality of field programmable gate arrays for reducing the skew of time delays. Another method is using the capability of programmable data path and loading of FPGA to create programmable delay line and controllable delays.

Encrypted Cryptography System
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US Patent:

8130945, Mar 6, 2012
Filed:

Oct 13, 2005
Appl. No.:

11/249892
Inventors:

Fong Luk - Alameda CA, US
International Classification:

H04K 1/00
US Classification:

380 28, 380260, 380267, 380268, 380282, 380285, 380 30, 380 1, 380200, 380243, 380247, 380251, 380255, 380277, 713171, 713189, 708255
Abstract:

A public key cryptography (PKI or other similar system) is used to sent partial or multiple of encryption or decryption algorithm (cipher or decipher) to the data sender or receiver to encrypt or decrypt the data to be sent or received and destroy itself after each or multiple use. Since the encryption algorithm is protected, it can be devised very small in size in compare to the data to be sent and the user can afford to use large key size in it's transmission to increase protection without significant compact to the overall speed. Without knowing the encryption algorithm, which may also be changing from time to time, it will be impossible to use brut force to break the code provided that the algorithm scheme is designed properly. It is due to that there are unlimited numbers of new or old algorithms with countless variations and it takes years of supper fast computing time to break even few algorithms. Under this condition, many fast encryption algorithms can be easily devised for use, thus speed and safety can be greatly enhanced.

Three Dimensional Seating Arrangement To Increase Seating Capacity
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US Patent:

20060060703, Mar 23, 2006
Filed:

Sep 22, 2004
Appl. No.:

10/948419
Inventors:

Fong Luk - Alameda CA, US
International Classification:

B64D 11/00
US Classification:

244118500
Abstract:

A method for arranging a plurality of seats in a moving vehicle, e.g., an airplane cabinet, is disclosed in this invention. The method includes a step of arranging at least two adjacent seats having two different elevation levels relative to a floor of said airplane cabinet. In a preferred embodiment, seats between two adjacent rows in the airplane cabinet having two different elevation levels. In another preferred embodiment, the method further includes a step of providing a space below a row of seats having a higher elevation to store a luggage therein.

Generation Of Test Vectors For Testing Electronic Circuits Taking Into Account Of Defect Probability
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US Patent:

20060095822, May 4, 2006
Filed:

Nov 1, 2004
Appl. No.:

10/979582
Inventors:

Fong Luk - Alameda CA, US
International Classification:

G01R 31/28
G06F 11/00
US Classification:

714738000
Abstract:

A method for generating test pattern signals weighted by the fault probability to greatly simplify the test process and to reduce the number of test vectors required for conducting the integrated circuit functionality tests. The method takes into consideration that the electrical short conditions occur mostly between adjacent nodes. The “fault coverage” concept is revised to test faults occurred between adjacent nodes and the test vectors are generated based a fault-probability weighted algorithm such that tests are conducted mostly on connections between adjacent nodes either on a same horizontal layer or on adjacent vertical layer having vertical overlapping areas.

Data Transferring System With Multiple Port Bus Connecting The Low Speed Data Storage Unit And The High Speed Data Storage Unit And The Method For Transferring Data
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US Patent:

56896700, Nov 18, 1997
Filed:

Oct 7, 1996
Appl. No.:

8/671106
Inventors:

Fong Luk - San Jose CA
International Classification:

G06F 938
G06F 1300
US Classification:

395383
Abstract:

A data processing system using a prefetch mechanism with high speed cache memory to increase the processing speed. Data is prefetched from a low speed main memory to the cache memory for data transfer instructions via multiple ports. For a program control transfer instruction, the prefetch mechanism prefetches instruction for each possible program path, stores them in the cache memory and continues with the prefetch processes.