Eugene Parrella

US Patent:

63213311, Nov 20, 2001

Filed:

Apr 22, 1998

Appl. No.:

9/064474

Inventors:

Subhash C. Roy - Stamford CT
Paul Hembrook - New Milford CT
Eugene L. Parrella - Monroe CT
Richard Mariano - Bethel CT

Assignee:

Transwitch Corporation - Shelton CT

International Classification:

G06F 930

US Classification:

712244

Abstract:

A debugging interface includes a pair of decoders and an event history buffer coupled to the sequencer of a processor. The first decoder is coupled to the program counter of the sequencer and the Instruction RAM of the processor. The second decoder is coupled to the cause register of the sequencer and the event history buffer is also coupled to the cause register. The first decoder provides a three bit real time output which is indicative of the processor activity on a cycle by cycle basis. The three bit output indicates seven different conditions: whether the last instruction executed by the processor was an inc, an exception, an exception with no event history buffer entry, or a branch taken, whether there has been no instruction executed since the last clock cycle, and whether a jump was an immediate jump or a jump to a register. The event history buffer is loaded with more detailed information about the instruction last executed when the first decoder indicates that the last instruction was an exception or a jump to a register, and when there is a change in state of an interrupt line or an internal processor exception. An exemplary implementation of the debugging interface is embodied on an ASIC chip having three processors.

US Patent:

61346535, Oct 17, 2000

Filed:

Apr 22, 1998

Appl. No.:

9/064446

Inventors:

Subhash C. Roy - Stamford CT
Paul Hembrook - New Milford CT
Eugene L. Parrella - Monroe CT
Richard Mariano - Bethel CT

Assignee:

TranSwitch Corp. - Shelton CT

International Classification:

G06F 948

US Classification:

712228

Abstract:

A RISC processor includes a sequencer, a register ALU (RALU), data RAM, and a coprocessor interface. The sequencer includes an N. times. 32 bit instruction RAM which is booted from external memory through the coprocessor interface. The RALU includes a four port register file for storage of three contexts, and an ALU. The ISA (instruction set architecture) according to the invention supports up to eight coprocessors. An important feature of the invention is that multiple sets of general purpose registers are provided for the storing of several contexts. According to a presently preferred embodiment, three sets of general purpose registers are provided as part of the RALU and a new opcode is provided for switching among the sets of general purpose registers. With multiple sets of general purpose registers, context switching can be completed in three processing cycles. In addition, one set of general purpose registers can be loaded by a coprocessor while another set of general purpose registers is in use by the ALU.

US Patent:

62466828, Jun 12, 2001

Filed:

Mar 5, 1999

Appl. No.:

9/263289

Inventors:

Subhash C. Roy - Stamford CT
Eugene L. Parrella - Shelton CT
Ian Ramsden - Woodbury CT

Assignee:

Transwitch Corp. - Shelton CT

International Classification:

H04L 1228

US Classification:

370390

Abstract:

Methods for managing multiple queues of ATM cells in shared RAM while efficiently supporting multicasting include providing a common memory for storing ATM cells and for storing at least one pointer to each ATM cell stored, providing a management memory for storing an index to the pointers stored in common memory, a table for each multicast session, and an index to the free space in common memory. According to the presently preferred method, cells entering the switch are examined, placed in shared RAM, and a pointer to the RAM location is written in another location in the shared RAM. Table entries in management RAM are updated each time a cell is added to a queue. When a multicast session is begun, a multicast table is created with all of the addresses in the multicast session. When a multicast cell is received, the multicast session table is consulted and pointers to the cell are copied to queues for each address in the table. When a pointer exits a queue, the cell pointed to by the pointer is read and transmitted to the address of the queue.