Erich Matthew Gens

US Patent:

7447966, Nov 4, 2008

Filed:

Jan 5, 2005

Appl. No.:

11/030349

Inventors:

Anand V. Kamannavar - Cincinnati OH, US
Nathan Dirk Zelle - Dallas TX, US
Bradley Forrest Bass - Carrollton TX, US
Sahir Shiraz Hoda - Plano TX, US
Erich Matthew Gens - Allen TX, US

Assignee:

Hewlett-Packard Development Company - Houston TX

International Classification:

G06F 11/00

US Classification:

714741, 714739, 714724, 714736, 714742, 714824, 714 25, 714 32, 714715, 703 14, 703 15, 702119, 716 1, 716 4, 716 5

Abstract:

Exemplary techniques for verifying a hardware design are described. In a described embodiment, a method comprises compiling an error verification object corresponding to an error verification command to verify a portion of a hardware design of a device under test. The error verification object is compiled in accordance with data provided by an error scripting module. The error scripting module has access to hardware-specific data corresponding to the hardware design of the device under test. The compiled object is sent to the device under test and a response to the compiled object is received from the device under test. The received response from the device under test is parsed in accordance with data provided by the error scripting module.