Eric H Laine

US Patent:

6438830, Aug 27, 2002

Filed:

Apr 15, 1999

Appl. No.:

09/292163

Inventors:

Eric P. Dibble - Endicott NY
Eric H. Laine - Binghamton NY
Stephen W. MacQuarrie - Vestal NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01R 4320

US Classification:

29876, 29842, 29844, 29861, 29852, 29837, 257697, 257766, 257774

Abstract:

A pinning process including the steps of gold-plating through-holes in a laminate carrier and crimping old or gold-plated pin located in the through-holes to form a pin head on the top and a pin bulge on the bottom of the laminate carrier to produce a plastic pin grid array. A variety of mechanical forming processes may be employed to form the pin heads and pin bulges and cause the pin to at least partially, and preferably substantially, fill and contact the gold-plated through-hole including swage pinning, impact pinning, and double-die pinning operations. By combining the steps of gold-plating through-holes of a laminate carrier and using a mechanical pinning process to crimp a gold or gold-plated pin in the through-holes, a reliable mechanical and electrical connection may be established between the pin and the metal lines both inside and on the surface of the laminate carrier without the need for lead-containing solders and pastes.

US Patent:

7932169, Apr 26, 2011

Filed:

Oct 5, 2009

Appl. No.:

12/587301

Inventors:

Luc Belanger - Granby, CA
Stephen L. Buchwalter - Hopewell Junction NY, US
Leena Paivikki Buchwalter - Hopewell Junction NY, US
Ajay P. Giri - Poughkeepsie NY, US
Jonathan H. Griffith - Lagrangeville NY, US
Donald W. Henderson - Ithaca NY, US
Sung Kwon Kang - Chappaqua NY, US
Eric H. Laine - Binghamton NY, US
Christian Lavoie - Pleasantville NY, US
Paul A. Lauro - Brewster NY, US
Valérie Anne Oberson - St-Alphonse de Granby, CA
Da-Yuan Shih - Poughkeepsie NY, US
Kamalesh K Srivastava - Wappingers Falls NY, US
Michael J. Sullivan - Red Hook NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/44

US Classification:

438612, 438613, 438614, 257779, 257781, 257E23021, 257E21509

Abstract:

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

US Patent:

8314500, Nov 20, 2012

Filed:

Dec 28, 2006

Appl. No.:

11/616919

Inventors:

Luc Belanger - Granby, CA
Stephen L. Buchwalter - Hopewell Junction NY, US
Leena Paivikki Buchwalter - Hopewell Junction NY, US
Ajay P. Giri - Poughkeepsie NY, US
Jonathan H. Griffith - Lagrangeville NY, US
Donald W. Henderson - Ithaca NY, US
Sung Kwon Kang - Chappaqua NY, US
Eric H. Laine - Binghamton NY, US
Christian Lavoie - Pleasantville NY, US
Paul A. Lauro - Brewster NY, US
Valérie Anne Oberson - St-Alphonse de Granby, CA
Da-Yuan Shih - Poughkeepsie NY, US
Kamalesh K Srivastava - Wappingers Falls NY, US
Michael J. Sullivan - Red Hook NY, US

Assignee:

Ultratech, Inc. - San Jose CA

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257779, 257753, 257761, 257766, 257780, 257E2302, 257E23021, 257E23023

Abstract:

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

US Patent:

59527161, Sep 14, 1999

Filed:

Apr 16, 1997

Appl. No.:

8/842859

Inventors:

Eric P. Dibble - Endicott NY
Eric H. Laine - Binghamton NY
Stephen W. MacQuarrie - Vestal NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23532

US Classification:

257697

Abstract:

A pinning process including the steps of gold-plating through-holes in a laminate carrier and crimping a gold or gold-plated pin located in the through-holes to form a pin head on the top and a pin bulge on the bottom of the laminate carrier to produce a plastic pin grid array. A variety of mechanical forming processes may be employed to form the pin heads and pin bulges and cause the pin to at least partially, and preferably substantially, fill and contact the gold-plated through-hole including swage pinning, impact pinning, and double-die pinning operations. By combining the steps of gold-plating through-holes of a laminate carrier and using a mechanical pinning process to crimp a gold or gold-plated pin in the through-holes, a reliable mechanical and electrical connection may be established between the pin and the metal lines both inside and on the surface of the laminate carrier without the need for lead-containing solders and pastes.

US Patent:

59397837, Aug 17, 1999

Filed:

May 5, 1998

Appl. No.:

9/072625

Inventors:

Eric Herman Laine - Binghamton NY
James Warren Wilson - Vestal NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2314
H01L 2348
H01L 2352
H05K 118

US Classification:

257702

Abstract:

An electronic package which includes a thermally conductive, e. g. , copper, member having a thin layer of dielectric material, e. g. , polyimide, on at least one surface thereof. On the polyimide is provided the desired high density circuit pattern which is electrically connected, e. g. , using solder or wirebonds, to the respective contact sites of a semiconductor chip. If wirebonds are used, the copper member preferably includes an indentation therein and the chip is secured, e. g. , using adhesive, within this indentation. If solder is used to couple the chip, a plurality of small diameter solder elements are connected to respective contact sites of the chip and to respective ones of the pads and/or lines of the provided circuit pattern. Significantly, the pattern possesses lines and/or pads in one portion which are of high density and lines and/or pads in another portion which are of lesser density. The chip is coupled to the higher density portion of the circuitry which then may "fan out" to the lesser (and larger) density lines and/or pads of the other portion of the circuitry.

US Patent:

56169582, Apr 1, 1997

Filed:

Jan 25, 1995

Appl. No.:

8/378347

Inventors:

Eric H. Laine - Binghamton NY
James W. Wilson - Vestal NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2334
H01L 23495
H01L 2348

US Classification:

257717

Abstract:

An electronic package which includes a thermally conductive, e. g. , copper, member having a thin layer of dielectric material, e. g. , polyimide, on at least one surface thereof. On the polyimide is provided the desired high density circuit pattern which is electrically connected, e. g. , using solder or wirebonds, to the respective contact sites of a semiconductor chip. If wirebonds are used, the copper member preferably includes an indentation therein and the chip is secured, e. g. , using adhesive, within this indentation. If solder is used to couple the chip, a plurality of small diameter solder elements are connected to respective contact sites of the chip and to respective ones of the pads and/or lines of the provided circuit pattern. Significantly, the pattern possesses lines and/or pads in one portion which are of high density and lines and/or pads in another portion which are of lesser density. The chip is coupled to the higher density portion of the circuitry which then may "fan out" to the lesser (and larger) density lines and/or pads of the other portion of the circuitry.

US Patent:

57510601, May 12, 1998

Filed:

Feb 4, 1997

Appl. No.:

8/795181

Inventors:

Eric Herman Laine - Binghamton NY
James Warren Wilson - Vestal NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2334
H01L 23495
H01L 2348

US Classification:

257702

Abstract:

An electronic package which includes a thermally conductive, e. g. , copper, member having a thin layer of dielectric material, e. g. , polyimide, on at least one surface thereof. On the polyimide is provided the desired high density circuit pattern which is electrically connected, e. g. , using solder or wirebonds, to the respective contact sites of a semiconductor chip. If wirebonds are used, the copper member preferably includes an indentation therein and the chip is secured, e. g. , using adhesive, within this indentation. If solder is used to couple the chip, a plurality of small diameter solder elements are connected to respective contact sites of the chip and to respective ones of the pads and/or lines of the provided circuit pattern. Significantly, the pattern possesses lines and/or pads in one portion which are of high density and lines and/or pads in another portion which are of lesser density. The chip is coupled to the higher density portion of the circuitry which then may "fan out" to the lesser (and larger) density lines and/or pads of the other portion of the circuitry.

US Patent:

57286060, Mar 17, 1998

Filed:

Mar 5, 1996

Appl. No.:

8/611299

Inventors:

Eric Herman Laine - Binghamton NY
James Warren Wilson - Vestal NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2160
H01L 2144

US Classification:

438122

Abstract:

An electronic package which includes a thermally conductive, e. g. , copper, member having a thin layer of dielectric material, e. g. , polyimide, on at least one surface thereof. On the polyimide is provided the desired high density circuit pattern which is electrically connected, e. g. , using solder or wirebonds, to the respective contact sites of a semiconductor chip. If wirebonds are used, the copper member preferably includes an indentation therein and the chip is secured, e. g. , using adhesive, within this indentation. If solder is used to couple the chip, a plurality of small diameter solder elements are connected to respective contact sites of the chip and to respective ones of the pads and/or lines of the provided circuit pattern. Significantly, the pattern possesses lines and/or pads in one portion which are of high density and lines and/or pads in another portion which are of lesser density. The chip is coupled to the higher density portion of the circuitry which then may "fan out" to the lesser (and larger) density lines and/or pads of the other portion of the circuitry.