Edvin Cetegen from Chandler, AZ, age 47

Resumes

Packaging Engineer

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Location:

3405 Tulane Dr, Hyattsville, MD 20783

Industry:

Semiconductors

Work:

Intel Corporation since Sep 2010
Packaging Engineer
Oak Ridge National Laboratory Apr 2010 - Sep 2010
Post Doc
University of Maryland Jun 2005 - Apr 2010
Research Assistant
Istanbul Technical University Jan 2001 - Jun 2005
Research Assistant
Demta Jun 2000 - Jan 2001
HVAC Project Engineer

Education:

University of Maryland College Park 2005 - 2009
PhD, Mechanical Engineering Istanbul Technical University 2000 - 2002
MS, Energy Istanbul Technical University 1996 - 2000
BS, Mechanical Engineering

Skills:

Heat Transfer
Cfd
Optimization
Thermodynamics
Fluid Mechanics
Matlab
Multiphase Flow
Labview

Languages:

English
Turkish
Romanian

Us Patents

Controlling Thermal Interface Material Bleed Out
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US Patent:

20140027899, Jan 30, 2014
Filed:

May 31, 2012
Appl. No.:

13/991900
Inventors:

Gopi Krishnan - Chandler AZ, US
Mingjie Xu - Chandler AZ, US
Edvin Cetegen - Chandler AZ, US
Sung-Won Moon - Phoenix AZ, US
International Classification:

H01L 23/34
US Classification:

257712, 438122
Abstract:

An extended preform of a thermal interface material (TIM) is formed between a heat spreader and a die on a substrate. The preform has an extension beyond a footprint of the die. The preform is cured. A bleed out of the TIM is controlled by the extension upon curing of the preform.

Microelectronic Structures Including Bridges
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US Patent:

20220199536, Jun 23, 2022
Filed:

Dec 18, 2020
Appl. No.:

17/126636
Inventors:

Omkar G. Karhade - Chandler AZ, US
Edvin Cetegen - Chandler AZ, US
Anurag Tripathi - Gilbert AZ, US
Nitin A. Deshpande - Chandler AZ, US
International Classification:

H01L 23/538
H01L 23/00
H01L 23/31
H01L 21/48
H01L 21/56
Abstract:

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Deformable Semiconductor Device Connection
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US Patent:

20230086180, Mar 23, 2023
Filed:

Sep 20, 2021
Appl. No.:

17/479854
Inventors:

- Santa Clara CA, US
Edvin Cetegen - Chandler AZ, US
Steve Cho - Chandler AZ, US
Nicholas S. Haehn - Scottsdale AZ, US
Jacob Vehonsky - Gilbert AZ, US
Gang Duan - Chandler AZ, US
International Classification:

H01L 23/00
Abstract:

A semiconductor device may include a first plate-like element having a first substantially planar connection surface with a first connection pad and a second plate-like element having a second substantially planar connection surface with a second connection pad corresponding to the first connection pad. The device may also include a connection electrically and physically coupling the first and second plate-like elements and arranged between the first and second connection pads. The connection may include a deformed elongate element arranged on the first connection pad and extending toward the second connection pad and solder in contact with the second connection pad and the elongate element.

Semiconductor Chip Package Having Internal I/O Structures With Modulated Thickness To Compensate For Die/Substrate Warpage
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US Patent:

20230086649, Mar 23, 2023
Filed:

Sep 23, 2021
Appl. No.:

17/483621
Inventors:

- Santa Clara CA, US
Edvin CETEGEN - Chandler AZ, US
Steve CHO - Chandler AZ, US
Nicholas S. HAEHN - Scottsdale AZ, US
Jacob VEHONSKY - Gilbert AZ, US
International Classification:

H01L 23/00
H01L 23/498
H01L 21/48
H01L 25/10
Abstract:

An apparatus is described. The apparatus includes I/O structures having pads and solder balls to couple with a semiconductor chip, wherein, a first subset of pads and/or solder balls of the pads and solder balls that approach the semiconductor chip during coupling of the semiconductor chip to the I/O structures are thinner than a second subset of pads and/or solder balls of the pads and solder balls that move away from the semiconductor chip during the coupling of the semiconductor chip to the I/O structures.

Microelectronic Structures Including Bridges
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US Patent:

20210391273, Dec 16, 2021
Filed:

Jun 16, 2020
Appl. No.:

16/902777
Inventors:

- Santa Clara CA, US
Omkar G. Karhade - Chandler AZ, US
Nitin A. Deshpande - Chandler AZ, US
Jinhe Liu - Chandler AZ, US
Sairam Agraharam - Chandler AZ, US
Mohit Bhatia - Chandler AZ, US
Edvin Cetegen - Chandler AZ, US
Assignee:

Interl Corporation - Santa Clara CA
International Classification:

H01L 23/538
H01L 23/498
H01L 23/00
Abstract:

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Microelectronic Structures Including Bridges
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US Patent:

20210391295, Dec 16, 2021
Filed:

Jun 16, 2020
Appl. No.:

16/902927
Inventors:

- Santa Clara CA, US
Nitin A. Deshpande - Chandler AZ, US
Mohit Bhatia - Chandler AZ, US
Sairam Agraharam - Chandler AZ, US
Edvin Cetegen - Chandler AZ, US
Anurag Tripathi - Gilbert AZ, US
Jan Krajniak - Mesa AZ, US
Manish Dubey - Chandler AZ, US
Jinhe Liu - Chandler AZ, US
Wei Li - Chandler AZ, US
Jingyi Huang - Chandler, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01L 23/00
H01L 23/538
H01L 23/498
Abstract:

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Underfill Flow Management In Electronic Assemblies
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US Patent:

20210343677, Nov 4, 2021
Filed:

Apr 29, 2020
Appl. No.:

16/862287
Inventors:

- Santa Clara CA, US
Taylor William Gaines - Chandler AZ, US
Edvin Cetegen - Chandler AZ, US
Wei Li - Chandler AZ, US
Hsin-Yu Li - Chandler AZ, US
Tony Dambrauskas - Chandler AZ, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01L 23/00
H01L 23/31
H01L 23/29
Abstract:

Disclosed herein are structures and techniques for underfill flow management in electronic assemblies. For example, in some embodiments, an electronic assembly may include a first component, a second component, an underfill on the first component and at least partially between the first component and the second component, and a material at a surface of the first component, wherein the material is outside a footprint of the second component, and the underfill contacts the material with a contact angle greater than 50 degrees.

Open Cavity Bridge Co-Planar Placement Architectures And Processes
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US Patent:

20210305132, Sep 30, 2021
Filed:

Mar 24, 2020
Appl. No.:

16/828405
Inventors:

- Santa Clara CA, US
Digvijay RAORANE - Chandler AZ, US
Sairam AGRAHARAM - Chandler AZ, US
Nitin DESHPANDE - Chandler AZ, US
Mitul MODI - Phoenix AZ, US
Manish DUBEY - Chandler AZ, US
Edvin CETEGEN - Chandler AZ, US
International Classification:

H01L 23/482
H01L 23/538
H01L 23/495
Abstract:

Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads. The package substrate also includes an open cavity between the first plurality of substrate pads and the second plurality of substrate pads, the open cavity having a bottom and sides. The electronic apparatus also includes a bridge die in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, and conductive traces. An adhesive layer couples the bridge die to the bottom of the open cavity. A gap is laterally between the bridge die and the sides of the open cavity, the gap surrounding the bridge die.