Edmundo J Rojas

US Patent:

6990538, Jan 24, 2006

Filed:

Jun 26, 2002

Appl. No.:

10/180675

Inventors:

Edmundo Rojas - Fort Collins CO, US
Hui-Sian Ong - West Wing, SG

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

G06F 3/00
H04L 1/00
H04L 12/28

US Classification:

710 14, 370225, 370431

Abstract:

A method and apparatus for managing a communication system including multiple links is presented. A receiver including a First-In, First-out (FIFO) memory receives information communicated on the links. A FIFO is associated with each communication link. Information is written into the FIFO based on a transmitter clock. Information is read out of the FIFO using a receiver clock. The FIFO is used to deskew data communicated across the communication links and re-synchronize the data between the transmitter clock and the receiver clock. A state machine controls the information read out of the FIFO. The state machine includes a deskew enabled state, a deskew disabled state and a reset state. Using the FIFO, the system is able to self reset and transition between the deskew enabled state and the deskew disabled state.

US Patent:

7082504, Jul 25, 2006

Filed:

Jul 19, 2002

Appl. No.:

10/199184

Inventors:

Edmundo Rojas - Fort Collins CO, US
Hui-Sian Ong - West Wing, SG

International Classification:

G06F 12/00

US Classification:

711154

Abstract:

A method and apparatus for operating a memory is presented. Information is stored in the memory based on a first time domain and information is read from the memory based on a second time domain. A cooperative relationship is maintained between a write pointer which points to memory locations, where data will be stored and a read pointer which points to memory locations, from which data will be read. A FIFO memory is presented which has memory locations and a register array is presented which stores a bit array that has bit locations. Each bit location in the bit array corresponds to a memory location in the memory. As the write pointer points to a memory location and data is stored in the memory location, a bit (e. g. flag) is set in the bit array. The Flag designates whether the data stored in the memory location is available for reading.

US Patent:

7209476, Apr 24, 2007

Filed:

Oct 12, 2001

Appl. No.:

09/977604

Inventors:

Ian Colloff - Los Gatos CA, US
Norman Chou - San Jose CA, US
Richard L. Schober - Cupertino CA, US
Mercedes Gil - Fort Collins CO, US
Edmundo Rojas - Fort Collins CO, US
Zhang Xiaoyang - San Jose CA, US

Assignee:

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore

International Classification:

H04L 12/50

US Classification:

370360

Abstract:

A networking system includes a plurality of ports, each adapted to send and receive data. A switch core has a first channel configured to receive a logical input flow from each of the plurality of input ports, and has a second channel configured to receive a raw input flow from each of the plurality of input ports. Each logical input flow is carried by its corresponding raw input flow. A plurality of port mirrors are selectable from the plurality of ports. Each of the plurality of port mirrors is configured to produce a duplicate copy of at least one of the logical input flow and the raw input flow available at a selected port.

US Patent:

7209478, Apr 24, 2007

Filed:

May 31, 2002

Appl. No.:

10/160938

Inventors:

Edmundo Rojas - Fort Collins CO, US
S. Paul Tucker - Ft. Collins CO, US

Assignee:

Palau Acquisition Corporation (Delaware) - Santa Clara CA

International Classification:

H04L 12/50

US Classification:

370360, 370359, 370389, 370412, 370351

Abstract:

A switch for use with an InfiniBand network. The switch includes a crossbar that redirects packet-based data based on a forwarding table. At least one port that receives data from a network and selectively transfers that data to the crossbar using a variable number of virtual lanes. A state machine controls the changing of the number of virtual lanes.

US Patent:

7313090, Dec 25, 2007

Filed:

Sep 26, 2002

Appl. No.:

10/255788

Inventors:

Edmundo Rojas - Fort Collins CO, US
S. Paul Tucker - Ft Collins CO, US
Mercedes E Gil - Fort Collins CO, US

Assignee:

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore

International Classification:

H04J 1/16

US Classification:

370229, 370235, 370400

Abstract:

In general, a system and method for providing data packet flow control is disclosed. Generally, a switch is provided that contains a series of ports, an arbiter and a hub. The arbiter determines an outgoing port, wherein the outgoing port is one port for the series of ports, for transmission of a data packet received by the switch, determines whether the outgoing port is available to receive the received data packet, and regulates transmission of the received data packet to a destination end node. The hub provides a point-to-point connection between any two of the series of ports and the arbiter.

US Patent:

7315542, Jan 1, 2008

Filed:

Sep 30, 2002

Appl. No.:

10/261012

Inventors:

Mercedes E Gil - Fort Collins CO, US
S. Paul Tucker - Ft Collins CO, US
Edmundo Rojas - Fort Collins CO, US

Assignee:

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore

International Classification:

H04L 12/28
H04L 1/18

US Classification:

370392, 370252, 370412, 370389, 714748

Abstract:

A method and structure for the handling and discarding of packets in a packet data network. The method includes a packet data network receiving one or more packets from one or more remote locations and initiating a transfer of a packet of the one or more packets to a remote destination. The remote destination is operable to act as a destination port of a switch. The transfer of the packet is initiated while the packet of the one or more packets is being received, and the packet validity is also checked while the transfer of the packet is initiated. If the packet is invalid, the transfer of the packet of the one or more packets to the remote destination is canceled. Determining packet validity includes inspection of a packet header. The structure has a receive link determining packet validity and passing this error signal to a packet processor. The packet processor has a packet transfer request generator, a packet checker, packet reader, packet memory and tag memory.

US Patent:

20030193894, Oct 16, 2003

Filed:

Apr 12, 2002

Appl. No.:

10/122455

Inventors:

S. Tucker - Ft Collins CO, US
Edmundo Rojas - Fort Collins CO, US

International Classification:

H04L012/26

US Classification:

370/235000, 709/229000

Abstract:

An early detection system is presented in which flow control logic is used to continually assess the capacity of a buffer memory. The flow control logic maintains an update of the buffer memory based on the buffer memories ability to store information associated with one of eight virtual lanes. As a result of the assessment, the flow control logic is capable of generating an early full detect signal. The early full detect signal denotes the capability of the buffer memory to hold packet information in a specific virtual lane. Packet checker logic receives the early full detect signal and assesses the first byte (e.g. first three bits) of a packet header, to determine whether the buffer memory can store information. If the packet passes the early detect test a second test is performed to determine if the buffer memory has enough space to store the packet. Should the buffer memory be unable to store information, the packet is discarded. If there is enough space in the buffer memory to store information, additional processing is performed to determine if the buffer memory has enough space to store the packet. As a result of the foregoing method and apparatus, several processing cycles are saved in processing the packet.

US Patent:

20030198240, Oct 23, 2003

Filed:

Apr 17, 2002

Appl. No.:

10/125154

Inventors:

Edmundo Rojas - Fort Collins CO, US

International Classification:

H04L012/28
H04L012/56

US Classification:

370/412000, 370/428000

Abstract:

A data-receiving port and method according to embodiments of the invention allow information concerning available buffer space in the receiving port of a communications channel to be transferred to a sending port. The timing of the information transferred can be programmed to depend on the status of previous data transfers from the sending port. This programmability allows the information transfers from the receiving port to be tailored to the specific characteristics of the data traffic being serviced. Therefore, the tradeoff between having enough information being transferred to a sending port to keep it apprised of the state of the buffer, and limiting that information so that data traffic from the receiving port to the sending port is not significantly impacted, can be managed effectively.

Address:

4438 Thompson Pkwy, Johnstown, CO 80534

Phone:

303 286-0943

VIN:

WDDGF7HB8AF488629

Make:

MERCEDES-BENZ

Model:

C-CLASS

Year:

2010