Dusan B Jevtic

US Patent:

6336204, Jan 1, 2002

Filed:

May 7, 1998

Appl. No.:

09/074122

Inventors:

Dusan Jevtic - Santa Clara CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 1, 700 97, 700100, 700101, 700102, 700103, 700121, 700213, 700120, 414936, 414937, 414939, 414940, 414941

Abstract:

A method and apparatus for handling deadlocks in a multichamber semiconductor wafer processing system known as a cluster tool. A plurality of software routines execute upon a sequencer of a cluster tool to perform deadlock avoidance, deadlock detection and deadlock resolution towards achieving optimal wafer throughput for a cluster tool.

US Patent:

6496746, Dec 17, 2002

Filed:

Mar 13, 2001

Appl. No.:

09/804808

Inventors:

Dusan Jevtic - Santa Clara CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

G06F 1900

US Classification:

700100, 700 99, 700101, 700102, 700121, 414217, 41422201, 41422501, 118719, 29 2501, 438907, 438908

Abstract:

A method and apparatus for producing schedules for a wafer in a multichamber semiconductor wafer processing tool comprising the steps of providing a trace defining a series of chambers that are visited by a wafer as the wafer is processed by the tool; initializing a sequence generator with a value of a variable defining initial wafer positioning within the tool; generating all successor variables for the initial variable value to produce a series of values of the variable that represent a partial schedule; backtracking through the series of variables to produce further partial schedules; and stopping the backtracking when all possible variable combinations are produced that represent all possible valid schedules for the trace. All the possible schedules are analyzed to determine a schedule that produces the highest throughput of all the schedules.

US Patent:

6519498, Feb 11, 2003

Filed:

Mar 10, 2000

Appl. No.:

09/523409

Inventors:

Dusan Jevtic - Santa Clara CA
Mark Pool - Sunnyvale CA
Raja Sunkara - Santa Clara CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

G06F 1900

US Classification:

700101, 700100, 700112, 700213

Abstract:

A method and apparatus for analyzing schedules for multi-cluster tools that are used in semiconductor wafer processing and similar manufacturing applications. The method and apparatus comprise a schedule analyzer and a pass-through chamber manager. The apparatus allows the user to analyze N!; possible scheduling routines (algorithms) for a given multi-cluster tool configuration and a given N-step process sequence. The invention derives a plurality of possible scheduling algorithms for a given set of input parameters and then compares the algorithms by allowing either the user or an automated process to assign each processing step within the proposed schedule a rank ordered priority. Other process or wafer movement parameters may also be given ranges such that the invention can automatically derive optimal schedules with respect to various parameter values. By comparing the results achieved with each scheduling algorithm, the method identifies the âbestâ schedule algorithm for a specific tool and tool parameters.

US Patent:

6580967, Jun 17, 2003

Filed:

Jun 26, 2001

Appl. No.:

09/893037

Inventors:

Dusan Jevtic - Santa Clara CA
Raja S. Sunkara - Santa Clara CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

G06F 700

US Classification:

700228, 700 99, 700213, 414806, 414940

Abstract:

A method and apparatus for providing distributed material management and flow control in an integrated circuit (IC) factory. The IC factory comprises a factory stocker, a plurality of process bays and a factory transport agent for moving wafer cassettes between the bay and the stocker. Each of the bays comprises a bay stocker, a plurality of tools, a mini-stocker and a bay transport agent for moving wafers amongst the bay components. The apparatus uses partitioned stockers to facilitate deadlock avoidance or deadlock resolution. Additionally, various algorithms are used to detect wafer cassette movement situations where deadlocks may result from a wafer cassette movement within a bay and for resolving deadlocks when they occur.

US Patent:

6684123, Jan 27, 2004

Filed:

Jun 26, 2001

Appl. No.:

09/893220

Inventors:

Dusan Jevtic - Santa Clara CA
Raja Sunkara - Santa Clara CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

G06F 1900

US Classification:

700121, 700 95, 700117, 438800, 414935, 414940

Abstract:

A factory interface for a multiple chamber semiconductor wafer processing cluster tool having a K-wafer load-lock (KWLL). The KWLL comprises a variable number of K+1 wafer slots assigned as inbound and outbound slots. Inbound slots are used to send up to K+1 wafers into the cluster tool and the same slots, denoted as outbound slots, are used for receiving up to K+1 wafers from the cluster tool. The K+1 slots are in the same volume that has to be pumped for wafers to enter the tool and vented for wafers that to leave the tool. These K+1 slots accommodate up to K wafers when accessed by a single blade robots from the tool or the factory interface, and up to K+1 wafers when the tool and factory interface are equipped with dual blade robots. Various KWLL loading methods can be selected to optimize the throughput of a wafer processing system using the KWLL. Such methods include wafer packing, reactive and gamma tolerant methods.

US Patent:

6725114, Apr 20, 2004

Filed:

Jan 26, 2001

Appl. No.:

09/771254

Inventors:

Dusan B. Jevtic - Santa Clara CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

G06F 1900

US Classification:

700100, 700 99, 700101

Abstract:

A method and apparatus for producing schedules for a wafer in a multichamber semiconductor wafer processing tool comprising the steps of providing a trace defining a series of chambers that are visited by a wafer as the wafer is processed by the tool; initializing a sequence generator with a vertex defining initial wafer positioning within the tool; generating all successor vertices to produce a series of vectors interconnecting the vertices that, when taken together produce a cycle that represents a schedule. All the possible schedules are analyzed to determine a schedule that produces the highest throughput of all the schedules.

US Patent:

6845294, Jan 18, 2005

Filed:

Jan 6, 2004

Appl. No.:

10/424330

Inventors:

Dusan Jevtic - Santa Clara CA, US
Raja S. Sunkara - Santa Clara CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

G06F 700

US Classification:

700228, 700 99, 700100, 700213, 414940

Abstract:

A method for providing distributed material management and flow control in an integrated circuit (IC) factory. The IC factory comprises a factory stocker, a plurality of process bays and a factory transport agent for moving wafer cassettes between the bay and the stocker. Each of the bays comprises a bay stocker, a plurality of tools, a mini-stocker and a bay transport agent for moving wafers amongst the bay components. The apparatus uses partitioned stockers to facilitate deadlock avoidance or deadlock resolution. Additionally, various algorithms are used to detect wafer cassette movement situations where deadlocks may result from a wafer cassette movement within a bay and for resolving deadlocks when they occur.

US Patent:

20020147960, Oct 10, 2002

Filed:

Jan 26, 2001

Appl. No.:

09/771255

Inventors:

Dusan Jevtic - Santa Clara CA, US
Raja Sunkara - Santa Clara CA, US

Assignee:

Applied Materials, Inc.

International Classification:

G06F017/50

US Classification:

716/019000

Abstract:

Apparatus and concomitant method for performing priority based scheduling of wafer processing within a multiple chamber semiconductor wafer processing system (cluster tool) having at least one metrology chamber. The sequencer assigns priority values to the chambers and stations in a wafer processing system (i.e., a cluster tool plus a factory interface), then moves wafers from chamber to chamber in accordance with the assigned priorities. The sequencer also selects particular wafers for placement into at least one metrology chamber or station.