Douglas J Doornink

US Patent:

43863671, May 31, 1983

Filed:

Jun 26, 1981

Appl. No.:

6/277788

Inventors:

James R. Peterson - Portland OR
Douglas J. Doornink - Portland OR

Assignee:

Tektronix, Inc. - Beaverton OR

International Classification:

H04N 502

US Classification:

358140

Abstract:

A system and method for receiving an input bit stream defining a non-interlaced video image and for producing concurrently an output bit stream defining an interlaced representation of such image. Intermediate storage of every other input raster line in a first-in/first-out oriented memory permits the output of the interlaced signal to be interleaved with the receipt of the non-interlaced input, and the interleaving of the input and output operations permits the use of a memory module having a capacity less than that required to store a complete raster line of input information. Provision is also made for synchronizing the output operation to U. S. or European standards.

US Patent:

41908341, Feb 26, 1980

Filed:

Oct 16, 1978

Appl. No.:

5/951703

Inventors:

Douglas J. Doornink - Portland OR

Assignee:

Tektronix, Inc. - Beaverton OR

International Classification:

G06F 314

US Classification:

340709

Abstract:

A circuit and method for receiving and sequentially decrementing the x and y coordinates of a desired cursor location so as to produce in a raster-scan display system a cross-hair cursor the component parts of which extend the full height and width of the display area.

US Patent:

50848305, Jan 28, 1992

Filed:

Oct 26, 1987

Appl. No.:

7/113045

Inventors:

Douglas J. Doornink - Portland OR
John C. Dalrymple - Portland OR

Assignee:

Tektronix, Inc. - Beaverton OR

International Classification:

G06F 314

US Classification:

395164

Abstract:

A memory device having a plurality of addressable memory locations, each of which can be defined uniquely by an address word having an X component and a Y component, which memory locations correspond respectively to grid points in a rectangular array at a pitch dX in the X direction and a pitch dY in the Y direction, is loaded with data values Q. In a first operating cycle, a first address word defining a memory location corresponding to a first grid point is generated. In a second cycle, a first value of Q as a function of X and Y is computed, and concurrently a second address word defining a memory location corresponding to a second grid point is generated. In a third cycle, the first value of Q is compared with a previous value of Q for the first grid point, and concurrently a third address word defining a memory location corresponding to a third grid point is generated and a second value of Q is computed. In a fourth cycle, the first value of Q is loaded into the memory location corresponding to the first grid point if that first value of Q bears a predetermined relationship to the previous value of Q.

US Patent:

51855992, Feb 9, 1993

Filed:

Jul 23, 1990

Appl. No.:

7/555979

Inventors:

Douglas J. Doornink - Portland OR
David L. Knierim - Wilsonville OR
John C. Dalrymple - Portland OR

Assignee:

Tektronix, Inc. - Wilsonville OR

International Classification:

G09G 536

US Classification:

340747

Abstract:

A high performance graphics display system for use as an engineering workstation includes a compact method of generating vectors and transmitting addresses for same from a picture processor to frame buffer control circuitry for writing or reading pixel values along the vector in the frame buffer. The system uses a multiplexed address/data bus. Off-screen memory in communication with the picture processor is used to store pixel data read along vectors in the frame buffer preceding writing a vector so that the original data can be restored when the written vector is moved or removed. Vectors are encoded by the picture processor as a first word containing the address of the beginning point of the vector and major axis and X and Y direction bits to indicate the vector's direction. A second word includes a minor axis bit, indicating whether the next pixel to be written or read is on or off the major axis, in the direction indicated for such axis in the first word. The first word also includes a hesitate bit indicating whether the first pixel of a vector is to be written or read.

US Patent:

41575377, Jun 5, 1979

Filed:

Apr 19, 1976

Appl. No.:

5/677947

Inventors:

Thomas B. Cheek - Portland OR
Douglas J. Doornink - Portland OR
Roger M. Handy - Hillsboro OR
David E. Heinen - Beaverton OR
Joseph H. Hubert - Wilsonville OR
Ronald J. Wilson - Oregon City OR

Assignee:

Tektronix, Inc. - Beaverton OR

International Classification:

G06F 314

US Classification:

340706

Abstract:

A system wherein dynamic capability is incorporated into direct view storage tube terminals to provide both refreshed and stored information. More specifically, the system incorporates dynamic picture capability into direct view storage tubes by utilizing a constant rate vector generator, a high speed deflection system and a local digital memory operating simultaneously to enable refreshed and stored vectors to be simultaneously displayed.

US Patent:

54520100, Sep 19, 1995

Filed:

Jul 18, 1994

Appl. No.:

8/276375

Inventors:

Douglas J. Doornink - Portland OR

Assignee:

Tektronix, Inc. - Wilsonville OR

International Classification:

H04N 1100
H04N 700

US Classification:

348497

Abstract:

A system for synchronizing asynchronous video signals with a reference signal for input to a digital video processing system has a first-in, first-out (FIFO) buffer for each input signal that writes the digitized video signal into the FIFO under control of an input clock signal derived from the digitized video signal, and reads the digitized video signal from the FIFO under control of the reference signal. An input state machine monitors the digitized video signal at the input and the occupancy of the FIFO to provide a write enable signal to the FIFO so long as the FIFO is not in danger of overflowing. An output state machine monitors the digitized video signal at the output and the occupancy of the FIFO to provide a read enable signal to the FIFO so long as the FIFO is not in danger of underflowing. When the FIFO is in danger of overflowing, the write enable signal is disabled during the blanking interval of the digitized video signal for a pre-determined number of pixels; and when the FIFO is in danger of underflowing, the read enable signal is disabled during the blanking interval of the digitized video signal for a pre-determined number of pixels.