Donald W Glowka from 236 2 Mile Ln, Flatonia, TX 78957, age 63, Phone: 512 581-2655

Resumes

Donald Glowka

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Skills:

Microsoft Office
Management
Microsoft Excel
Microsoft Word
Research
Powerpoint
Sales
Leadership
Training
Photoshop

Us Patents

Generation Of Route Rules
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US Patent:

6732346, May 4, 2004
Filed:

May 24, 2002
Appl. No.:

10/155042
Inventors:

Stephen C. Horne - Austin TX
Gopal Vijayan - Austin TX
Donald W. Glowka - Austin TX
Assignee:

Intrinsity, Inc. - Austin TX
International Classification:

G06F 1750
US Classification:

716 12, 716 1
Abstract:

This invention discloses a software tool that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device. The software tool includes a routing rule generation tool that creates a route rule database for a given semiconductor fabrication technology and circuit family of logic gates, and includes a block build tool that interconnects the logic gates with routes according to the route rules generated by the routing rule generation tool. The routing rule generation tool further includes a noise sensitivity/gate characterization tool and a rule generator tool. The block build tool further includes a gate sizing tool , a gate analysis tool , a route rule selecting tool , a route assigning tool.

Physical Realization Of Dynamic Logic Using Parameterized Tile Partitioning
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US Patent:

7219326, May 15, 2007
Filed:

Dec 16, 2003
Appl. No.:

10/738278
Inventors:

Jeffrey B. Reed - Austin TX, US
James S. Blomgren - Austin TX, US
Donald W. Glowka - Austin TX, US
Timothy A. Olson - Austin TX, US
Thomas W. Rudwick - Austin TX, US
Assignee:

Intrinsity, Inc. - Austin TX
International Classification:

G06F 17/50
US Classification:

716 18, 716 5
Abstract:

The matching algorithm of the layout synthesis method and apparatus disclosed locates transistor pattern matches in a design, links a parameterized tile to each identified match, and adjusts certain variable parameters of the linked parameterized tile to meet the physical design requirements of each located match. Each transistor pattern corresponds to a parameterized tile, which is an actual physical representation of the corresponding pattern and includes variable parameters, which may include transistor size. The matching algorithm locates matches in the design for an ordered list of patterns, names each located match, links the proper parameterized tile to each named match, and adjusts the tile's variable parameters as required. Transistors in the design are included in one and only one named located match.

Method For Manipulating And Repartitioning A Hierarchical Integrated Circuit Design
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US Patent:

8397190, Mar 12, 2013
Filed:

Aug 2, 2011
Appl. No.:

13/196005
Inventors:

Robert D. Kenney - Austin TX, US
Raymond C. Yeung - Round Rock TX, US
Paul K. Miller - Dripping Springs TX, US
Donald W. Glowka - Austin TX, US
Jeffrey B. Reed - Austin TX, US
Assignee:

Apple Inc. - Cupertino CA
International Classification:

G06F 17/50
US Classification:

716106, 716110, 716124, 716126, 716131, 716132, 716136, 716138, 716139, 703 13, 703 14
Abstract:

A hardware description language representation of an original circuit block containing one or more hierarchies may be obtained. Some, or all of the hierarchies may be dissolved to access each circuit component within the original circuit block at a same level of hierarchy. Designated circuit components may then be grouped together to create new circuit blocks at a new level of hierarchy. Components and signals within each new circuit block may be renamed to match logically corresponding components and signals within each other new circuit block. Missing pins may be added for each new circuit block, and connected to respective associated signals within the new circuit block, and logically equivalent pins may be given the same name to ensure the new circuit blocks are logically equivalent to each other and have identical interfaces. One of the new circuit blocks may be selected for physical build to obtain one or more physical instances corresponding to the selected new circuit block, and a top-level build may link each new circuit block instance to one of those one or more physical instances.

Method For Calculating Dynamic Logic Block Propagation Delay Targets Using Time Borrowing
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US Patent:

20020067187, Jun 6, 2002
Filed:

Apr 27, 2001
Appl. No.:

09/844686
Inventors:

Gopal Vijayan - Austin TX, US
James Blomgren - Austin TX, US
Donald Glowka - Austin TX, US
Stephen Horne - Austin TX, US
Assignee:

Intrinsity, Inc. - Austin TX
International Classification:

H03K019/00
US Classification:

326/093000
Abstract:

The present invention is a dynamic logic propagation delay targeting tool that includes a gate target delay initializer a levelizer a backward logic scanner a forward logic scanner a gate target delay incrementor and a gate target delay comparator that together calculates the propagation delay of a signal in a specified block of dynamic logic.