Donald E Clay

US Patent:

20030130073, Jul 10, 2003

Filed:

Jan 7, 2002

Appl. No.:

10/036904

Inventors:

Donald Clay - Grand Junction CO, US

International Classification:

A63B069/00
A63B069/38

US Classification:

473/460000

Abstract:

An apparatus for sweeping and collecting ball-like objects from a horizontal surface. The surface bears much if not all of the weight of the collected objects. An essential feature of this invention is a flexible strap connected across the opening of an object-collection space. The strap serves to facilitate collection and retention of the ball-like objects. The object-collection space is defined by a sweeping frame in a concave shape with an opening in the direction of the sweeping motion. The flexible strap is connected in tension across the opening in order to facilitate the collection and retention of the objects.

US Patent:

54126665, May 2, 1995

Filed:

Dec 29, 1992

Appl. No.:

7/997898

Inventors:

John P. Squires - Boulder CO
Charles M. Sander - Longmont CO
Stanton M. Keeler - Longmont CO
Donald W. Clay - Louisville CO

Assignee:

Conner Peripherals, Inc. - San Jose CA

International Classification:

G06F 1110

US Classification:

371 374

Abstract:

A multi-layer data integrity system for use in a disk drive controller for ensuring the data integrity as data is transferred through the controller and written and fetched from the disk media. The disk drive controller is partitioned into an interface controller and a low level controller where the interface controller controls the transfer of data to and from the host processor and the low level controller controls the recording and reading from the disk media. The interface controller employs a first error encoding and detecting means for encoding the data as originally received from the host processor. The low level controller employs an error encoding and detecting means for encoding both the received data and the encoding data which was appended to the data received by the interface controller. The low level controller's error encoding and detecting means corrects errors detected in recovered data. The interface controller during a fetch operation receives the data from the low level controller and determines if the data is valid and whether the data received from the low level controller was in fact the data being sought by the interface controller.

US Patent:

52747735, Dec 28, 1993

Filed:

Dec 29, 1992

Appl. No.:

7/997860

Inventors:

John P. Squires - Boulder CO
Charles M. Sander - Longmont CO
Stanton M. Keeler - Longmont CO
Donald W. Clay - Louisville CO

Assignee:

Conner Peripherals, Inc. - San Jose CA

International Classification:

G06F 1314

US Classification:

395275

Abstract:

A high level controller for maintaining communication with a host processor via a host processor interface for establishing communication paths between the host processor interface, an internal processor and a plurality of storage means. A first means receives indicia from the internal processor where the indicia specifies one of the communication paths and generates control signals for forming the specific communication path requested. A second means receives the control signals from the first means and forms the requested communication path. A third means is connected to the first and second means for controlling the communication of the system with the host processor interface in accordance with control signals generated by the first means. In this manner various data paths for communication between the host interface, internal processor and a plurality of storage means may be adaptably specified and formed to make optimum use of the system.

US Patent:

56108087, Mar 11, 1997

Filed:

Sep 29, 1994

Appl. No.:

8/315129

Inventors:

John P. Squires - Boulder CO
Charles M. Sander - Longmont CO
Stanton M. Keeler - Longmont CO
Donald W. Clay - Louisville CO

Assignee:

Conner Peripherals, Inc. - San Jose CA

International Classification:

G05B 1502

US Classification:

364131

Abstract:

A controller in a hard disk drive system for controlling the transfer of data and control signals between a plurality of host processors and the disk drive system. The disk drive system including storage media, at least one transducer for recording data on and retrieving data from the storage media and an actuator for moving the transducers with respect to the storage media. The controller includes a programmed first microprocessor operating under control of a first operating system stored in a first memory unit associated with the first microprocessor for controlling the recording of data on and the retrieval of data from the storage media, the controlling of the actuator to locate the transducer at and to maintain the transducer at a specified location with respect to the storage media. The controller includes a programmed second microprocessor operating under control of a second operating system stored in a second memory unit associated with the second microprocessor for controlling the transfer of data from a requesting host processor to the disk drive system and the transfer of data recovered from the storage media to a requesting host processor and for generating and communicating parameters to the first microprocessor for defining operations to be performed by the first microprocessor. The second microprocessor operates independently of and concurrently with the first microprocessor and the first microprocessor operates independently of and concurrently with the second microprocessor in exercising operations defined by the parameters received from the second microprocessor.

US Patent:

52610586, Nov 9, 1993

Filed:

Mar 5, 1993

Appl. No.:

8/027614

Inventors:

John P. Squires - Boulder CO
Charles M. Sander - Longmont CO
Stanton M. Keeler - Longmont CO
Donald W. Clay - Louisville CO

Assignee:

Conner Peripherals, Inc. - San Jose CA

International Classification:

G06F 1314

US Classification:

395275

Abstract:

A disk drive architecture controls the transfer of data between a host processor interface and a recording media that includes one or more disk surfaces for storing data. A low-level data controller controls the transfer of data between the disk surfaces and a data buffer. An interface controller controls the transfer of data between the host interface and the data buffer. An arbiter and buffer controller, responsive to data transfer requests from the low-level and interface controllers, arbitrates data storage and retrieval accesses of the data buffer. The low-level and interface controllers operate substantially independent of one another in performing their respective control operations. Consequently, data is transferred bi-directionally through the data buffer at the optimum timing for both controllers.

US Patent:

54598508, Oct 17, 1995

Filed:

Feb 19, 1993

Appl. No.:

8/019860

Inventors:

Donald W. Clay - Louisville CO
Steven A. Anderson - Loveland CO

Assignee:

Conner Peripherals, Inc. - San Jose CA

International Classification:

G06F 1206
G06F 1204

US Classification:

39549702

Abstract:

A flash solid state drive, having a flash solid state memory compatible with ATA/IDE Interface standards to be connected to a host for storing or retrieving sectors of data, where each sector contains 512 bytes of data, each sector is addressed by a cylinder, head and sector number CHS. The host provides, for a read or write operation, the number of sectors to be stored or retrieved, the CHS for each sector to be stored or retrieved and the data for the sectors to be stored. The solid state memory has stored therein a header for each CHS address that can be issued by the host, the header having indicia identifying the data block and indicating where the data for the data block is stored in the solid state memory. The flash solid state device comprises a translator means for translating the CHS address into a logic sector number LSN for identifying sectors in the flash solid state drive and a controller for converting sectors received from the host into variable length sectors to be stored in the flash solid state memory.

US Patent:

54653380, Nov 7, 1995

Filed:

Aug 24, 1993

Appl. No.:

8/110883

Inventors:

Donald W. Clay - Louisville CO

Assignee:

Conner Peripherals, Inc. - San Jose CA

International Classification:

G06F 1300

US Classification:

395310

Abstract:

In a disk drive storage system, an interface apparatus for controlling the transfer of sectors of data between a host processor and a buffer within the storage system in response to READ and WRITE command issued by the host processor. The apparatus comprises a Byte Count State Machine for controlling the transfer of a sector of data between the host processor and the buffer, an Update Task File State Machine for counting the sectors transferred by the Byte Count State Machine and generating the sector address of the next sector to be transferred by the Byte Count State Machine, a Read State Machine for controlling the processing of all READ commands and a Write State Machine for controlling the processing of all WRITE commands.

US Patent:

61700312, Jan 2, 2001

Filed:

Jul 8, 1997

Appl. No.:

8/889360

Inventors:

Donald Clay - Louisville CO

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

G06F 1300

US Classification:

710130

Abstract:

In a storage system such as an ATA compatible flash disk drive, it is common to use state machines to automate the transfer of data between a buffer in the storage system and the host processor. Four state machines are typically provided: an Update Task File state machine, a Byte Count state machine, a Read State Machine, and a Write State Machine. In the prior art, the Read and Write State machines did not allow the microcontroller to intervene between transfers of sectors or blocks in multiple (blocked) commands. Furthermore, the prior art Read State Machine and Write State Machine did not allow for the automation of DMA commands. Finally, the prior art Read State Machine and Write State Machine required too much time between sectors and between blocks. Therefore, an improved Read State Machine and an improved Write State Machine are provided which allow the microcontroller to intervene between transfers, allow the automation of DMA commands, and reset outstanding commands which are active. Furthermore, the Read State Machine and Write State Machine of the present invention require fewer state times between sectors, allowing faster data transfers.