Donald George Bartlett

US Patent:

6476736, Nov 5, 2002

Filed:

Aug 27, 2001

Appl. No.:

09/941245

Inventors:

Donald M. Bartlett - Fort Collins CO

Assignee:

Applied Micro Circuits Corporation - Fort Collins CO

International Classification:

H03M 502

US Classification:

341 56, 341 57, 341 61, 341102, 341103

Abstract:

Disclosed is transmission of a signal over a single interconnect between functional blocks of the IC. A scaled or encoded signal responsive to a first digital signal is generated by summing currents responsive to the first control signal. The summed currents, which may be the sum of one or more currents, is the scaled signal. The encoded signal is transmitted over a single interconnect. This transmission occurs in one clock period in contrast to the at least two clock periods required to serially transmit data. The encoded signal is then used to generate a second digital signal. The generation of the second digital signal preferably includes mirroring the current of the encoded signal. The mirrored current is can then generate one or more separate voltages which are used to generate the second digital signal.

US Patent:

6885078, Apr 26, 2005

Filed:

Nov 9, 2001

Appl. No.:

09/991277

Inventors:

Donald M. Bartlett - Fort Collins CO, US
Gayle W. Miller - Colorado Springs CO, US
Randall J. Mason - Colorado Springs CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L029/00

US Classification:

257499, 257133, 257256, 257263, 257265, 257272, 257798, 257920, 438514, 438526, 438942, 438948

Abstract:

A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across the substrate. The embedded ions provide low resistance regions that allow injected currents from a circuit to flow directly to a ground potential in the same circuit rather than flowing across the substrate to other circuits. High energy implantation processes on the order of 1 MeV to 3 MeVs can be used to implant the ions in embedded regions. Multiple energy levels can be used to provide thick embedded layers either prior to or after application of an epitaxial layer. Various masking materials can be used to mask the isolation regions during the implantation process, including hard masking materials such as silicon dioxide or silicon nitride, poly-silicon or an amorphous silicon layer, and a photoresist layer. Additive materials can be used in one or more of the masking layers to increase the absorption characteristics of the high energy ions.

US Patent:

7683672, Mar 23, 2010

Filed:

Sep 10, 2008

Appl. No.:

12/208040

Inventors:

Donald Bartlett - Fort Collins CO, US

International Classification:

H03K 19/094
H03K 5/12

US Classification:

326 83, 327170, 330296

Abstract:

Disclosed is a dynamically controlled, output slew rate pad driver that generates a controlled voltage on an interface node of an interface circuit, such as an input circuit, an output circuit, or a combined input/output circuit, to control the process of slewing the controlled voltage on the interface node. The slewing occurs substantially independently of capacitive loads connected to the interface node. Prior to initiation of the slewing process, an initial charge is generated on a storage capacitor. The storage capacitor is then connected to the gate of a driver transistor to charge the input parasitic gate capacitance of the driver transistor to approximately a gate threshold voltage of the driver transistor. A constant current source is also provided that is applied to the input of an integrating amplifier and an integrating capacitor that is connected to the interface node. The constant current is integrated to provide a controlled, slewed voltage on the interface node by charging the integrating capacitor with a constant current from the constant current source.

US Patent:

59146176, Jun 22, 1999

Filed:

Dec 23, 1996

Appl. No.:

8/772617

Inventors:

Donald M. Bartlett - Fort Collins CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03K 190185

US Classification:

326 81

Abstract:

An on-chip driver is described for applications voltage output signals are desired from a digital sub-micron CMOS integrated circuit. The driver includes a signal buffer, signal level shifter, output pull-up, and an output pull-down. The signal buffer is coupled to a digital CMOS input for generating a corresponding buffered signal that is received by both the output-up down and the level shifter. The output pull-down is responsive to the buffered signal and operates to pull the output of the driver to a low voltage level of about 0 volts when the digital CMOS input is at a low logic state. Further, the level shifter is responsive to the buffered signal for generating a voltage shifted signal that is received by the pull-up which pulls the output of the driver to a high voltage level of 2. 5 volts or greater when the digital CMOS input is at a high logic state.

US Patent:

56082738, Mar 4, 1997

Filed:

Nov 25, 1991

Appl. No.:

7/796992

Inventors:

Donald M. Bartlett - Fort Collins CO

Assignee:

AT&T Global Information Solutions Company - Dayton OH
Hyundai Electronics America - San Jose CA
Symbios Logic Inc. - Fort Collins CO

International Classification:

H02J 906

US Classification:

307 64

Abstract:

The invention concerns battery back-up for electronic equipment. A sensor detects a drop in power supply voltage and, in response, connects the back-up battery to the equipment, via a Field-Effect Transistor (FET). The FET causes a lower voltage drop between the battery and the equipment, as compared with a commonly used alternative, namely, a diode.

US Patent:

52870707, Feb 15, 1994

Filed:

Sep 2, 1992

Appl. No.:

7/939225

Inventors:

Bob Thelen - Fort Collins CO
Donald M. Bartlett - Fort Collins CO

Assignee:

NCR Corporation - Dayton OH

International Classification:

H03F 345

US Classification:

330253

Abstract:

A biasing system for a CMOS differential comparator includes a unity gain amplifier for developing a reference voltage corresponding to the trip point of an output inverter. The reference voltage is applied to a voltage to current converter for developing a reference current proportional to the reference voltage. The reference current biases the output inverters at their trip points when the input voltages to the differential comparator are at the same potential. The biasing system includes a reference inverter having characteristics substantially identical to the output inverters. The output and input of the reference inverter are connected together so that a reference voltage is established at the inverter output which is always at the switch point of the inverter. A differential transistor stage includes resistive loads matched in process characteristics and sized to each pass one-half the value of the reference current to reduce the load capacitance at the differential stage. An output stage of the comparator circuit uses a source follower with characteristics matching those of the voltage to current converter so that the output nodes at the source follower have the same value as the reference voltage.

US Patent:

54324408, Jul 11, 1995

Filed:

Nov 25, 1991

Appl. No.:

7/796995

Inventors:

Donald M. Bartlett - Fort Collins CO

Assignee:

AT&T Global Information Solutions Company - Dayton OH
Hyundai Electronics America - Milpitas CA

International Classification:

G01R 1512

US Classification:

3241581

Abstract:

The invention concerns utilization of a single pin on an integrated circuit for a dual purpose. First, the pin carries data in a normal manner. Second, the pin carries a test signal, which is used, for example, to trigger a testing circuit into action. The invention receives both the data signals and the test signal. The invention ignores the data signals, and responds only to the test signals.

US Patent:

56002173, Feb 4, 1997

Filed:

Nov 22, 1994

Appl. No.:

8/343275

Inventors:

Donald M. Bartlett - Fort Collins CO

Assignee:

AT&T Global Information Solutions Company - Dayton OH
Hyundai Electronics America - San Jose CA
Symbios Logic Inc. - Fort Collins CO

International Classification:

H02P 300

US Classification:

318434

Abstract:

A CMOS disk drive motor control circuit which has back-EMF regulator circuitry which prevents the back-EMF from the disk drive motor from exceeding a predetermined level. The back-EMF provides an alternate power source for parking the read/write head when power is removed from the disk drive. The circuit is fabricated as a single CMOS integrated circuit which is coupled between a power supply and the disk drive motor. The disk drive control circuit also includes a blocking diode through which power from the power supply flows to the motor and which prevents dissipation of a back-EMF from the motor when power is removed from the motor, and disk drive head parking circuitry which uses the back-EMF to retract and park the disk drive head.

Author:

Donald Bartlett

ISBN #:

0122930606

Author:

Donald A. Bartlett

ISBN #:

0872630277

Author:

Donald L. Bartlett

ISBN #:

0393075133