Derrick Pojen Lin

US Patent:

6507904, Jan 14, 2003

Filed:

Mar 31, 2000

Appl. No.:

09/541477

Inventors:

Carl M. Ellison - Portland OR
Roger A. Golliver - Beaverton OR
Howard C. Herbert - Phoenix AZ
Derrick C. Lin - Foster City CA
Francis X. McKeen - Portland OR
Gilbert Neiger - Portland OR
Ken Reneris - Wilbraham MA
James A. Sutton - Portland OR
Shreekant S. Thakkar - Portland OR
Millind Mittal - Palo Alto CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 944

US Classification:

712229, 711152, 709100

Abstract:

A technique is provided to execute isolated instructions according to an embodiment of the present invention. An execution unit executes an isolated instruction in a processor operating in a platform. The processor is configured in one of a normal execution mode and an isolated execution mode. A parameter storage containing at least one parameter to support execution of the isolated instruction when the processor is configured in the isolated execution mode.

US Patent:

6631389, Oct 7, 2003

Filed:

Dec 22, 2000

Appl. No.:

09/747122

Inventors:

Derrick Chu Lin - Foster City CA
Punit Minocha - Santa Clara CA
Alexander D. Peleg - Haifa, IL
Yaakov Yaari - Haifa, IL
Millind Mittal - South San Francisco CA
Larry M. Mennemeier - Boulder Creek CA
Benny Eitan - Haifa, IL

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 501

US Classification:

708209

Abstract:

An apparatus for performing a shift operation on a packed data element having a multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.

US Patent:

6631452, Oct 7, 2003

Filed:

Apr 28, 2000

Appl. No.:

09/561145

Inventors:

Derrick Lin - San Mateo CA

Assignee:

Idea Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

711159, 711154

Abstract:

A computer system is provided having a register stack engine to manage data transfers between a backing store and a register stack. The computer system includes a processor and a memory coupled to the processor through a memory channel. The processor includes a register stack to store data from one or more procedures in one or more frames, respectively. The register stack engine monitors activity on the memory channel and transfers data between selected frames of the register stack and a backing store in the memory responsive to the available bandwidth on the memory channel.

US Patent:

6633963, Oct 14, 2003

Filed:

Jul 18, 2000

Appl. No.:

09/618489

Inventors:

Carl M. Ellison - Portland OR
Roger A. Golliver - Beaverton OR
Howard C. Herbert - Phoenix AZ
Derrick C. Lin - San Mateo CA
Francis X. McKeen - Portland OR
Gilbert Neiger - Portland OR
Ken Reneris - Wilbraham MA
James A. Sutton - Portland OR
Shreekant S. Thakkar - Portland OR
Millind Mittal - Palo Alto CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1206

US Classification:

711163, 711153, 711152, 711170, 711173

Abstract:

A processor having a normal execution mode and an isolated execution mode generates an access transaction. The access transaction is configured using a configuration storage that stores configuration settings. The configuration settings include a plurality of subsystem memory range settings defining memory zones. The access transaction also includes access information. A multi-memory zone access checking circuit, coupled to the configuration storage, checks the access transaction using at least one of the configuration settings and the access information. The multi-memory zone access checking circuit generates an access grant signal if the access transaction is valid.

US Patent:

6678825, Jan 13, 2004

Filed:

Jul 18, 2000

Appl. No.:

09/618738

Inventors:

Carl M. Ellison - Portland OR
Roger A. Golliver - Beaverton OR
Howard C. Herbert - Phoenix AZ
Derrick C. Lin - San Mateo CA
Francis X. McKeen - Portland OR
Gilbert Neiger - Portland OR
Ken Reneris - Wilbraham MA
James A. Sutton - Portland OR
Shreekant S. Thakkar - Portland OR
Millind Mittal - Palo Alto CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1760

US Classification:

713200, 711152, 711163, 710200

Abstract:

The present invention provides a method, apparatus, and system for controlling memory accesses to multiple isolated memory areas in an isolated execution environment. A page manager is used to distribute a plurality of pages to a plurality of different areas of a memory, respectively. The memory is divided into non-isolated areas and isolated areas. The page manager is located in an isolated area of memory. Further, a memory ownership page table describes each page of memory and is also located in an isolated area of memory. The page manager assigns an isolated attribute to a page if the page is distributed to an isolated area of memory. On the other hand, the page manager assigns a non-isolated attribute to a page if the page is distributed to a non-isolated area of memory. The memory ownership page table records the attribute for each page. In one embodiment, a processor having a normal execution mode and an isolated execution mode generates an access transaction.

US Patent:

6738793, May 18, 2004

Filed:

Feb 14, 2001

Appl. No.:

09/783816

Inventors:

Derrick Chu Lin - Foster City CA
Punit Minocha - Sunnyvale CA
Alexander D. Peleg - Haifa, IL
Yaakov Yaari - Haifa, IL
Millind Mittal - Palo Alto CA
Larry M. Mennemeier - Boulder Creek CA
Benny Eitan - Haifa, IL
Srinivas Chennupaty - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 505

US Classification:

708209, 712223

Abstract:

An apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.

US Patent:

6754815, Jun 22, 2004

Filed:

Jul 18, 2000

Appl. No.:

09/618659

Inventors:

Carl M. Ellison - Portland OR
Roger A. Golliver - Beaverton OR
Howard C. Herbert - Phoenix AZ
Derrick C. Lin - San Mateo CA
Francis X. McKeen - Portland OR
Gilbert Neiger - Portland OR
Ken Reneris - Wilbraham MA
James A. Sutton - Portland OR
Shreekant S. Thakkar - Portland OR
Millind Mittal - Palo Alto CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 15177

US Classification:

713 1, 713 2

Abstract:

The present invention provides a method, apparatus, and system for invoking a reset process in response to a processor being individually reset. The reset processor operates within a platform in an isolated execution mode and is associated with an isolated area of memory. An initialization process is invoked for an initializing processor. The initialization process determines whether or not a cleanup flag is set. If the cleanup flag is set, the isolated area of memory is scrubbed. In one embodiment, when a last processor operating in the platform is reset, it is reset without clearing the cleanup flag. Subsequently, an initializing processor invokes the initialization process. The initialization process determines that the cleanup flag is set. The initialization process invokes the execution of a processor nub loader. If the cleanup flag is set, the processor nub loader scrubs the isolated area of memory and invokes a controlled close for the initializing processor.

US Patent:

6760441, Jul 6, 2004

Filed:

Mar 31, 2000

Appl. No.:

09/539348

Inventors:

Carl M. Ellison - Portland OR
Roger A. Golliver - Beaverton OR
Howard C. Herbert - Phoenix AZ
Derrick C. Lin - Foster City CA
Francis X. McKeen - Portland OR
Gilbert Neiger - Portland OR
Ken Reneris - Wilbraham MA
James A. Sutton - Portland OR
Shreekant S. Thakkar - Portland OR
Millind Mittal - Palo Alto CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 900

US Classification:

380 45, 380 44

Abstract:

The present invention is a method, apparatus, and system to generate a key hierarchy for use in an isolated execution environment of a protected platform. In order to bind secrets to particular code operating in isolated execution, a key hierarchy comprising a series of symmetric keys for a standard symmetric cipher is utilized. The protected platform includes a processor that is configured in one of a normal execution mode and an isolated execution mode. A key storage stores an initial key that is unique for the platform. A cipher key creator located in the protected platform creates the hierarchy of keys based upon the initial key. The cipher key creator creates a series of symmetric cipher keys to protect the secrets of loaded software code.