Grant B. Richards - Meridian ID Delnis L. Miranda - Fremont CA
Assignee:
Zilog, Inc. - Campbell CA
International Classification:
G06F 1300
US Classification:
395821
Abstract:
A dual latch character pacing circuit on a semiconductor chip controls data transfer between a pair of microprocessor which have significantly different data transfer rates. A first and second latch are connected in a parallel data path between the two microprocessor. The timing circuit includes a flip-flop which clocks the data between the latches. A one-shot timer is re-started on each transfer of data thereby insuring that the rate of transfer is substantially constant over a character period.