Debby A Eades

US Patent:

7749829, Jul 6, 2010

Filed:

May 1, 2007

Appl. No.:

11/742755

Inventors:

Gauri V. Karve - Austin TX, US
Debby Eades - Manor TX, US
Gregory S. Spencer - Pflugerville TX, US
Ted R. White - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/336

US Classification:

438198, 438222, 438404, 438481, 257E216

Abstract:

A semiconductor process and apparatus provides a planarized hybrid substrate () by removing a nitride mask layer () and using an oxide polish stop layer () when an epitaxial semiconductor layer () is being polished for DSO and BOS integrations. To this end, an initial SOI wafer semiconductor stack () is formed which includes one or more oxide polish stop layers () formed between the SOI semiconductor layer () and a nitride mask layer (). The oxide polish stop layer () may be formed by depositing a densified LPCVD layer of TEOS to a thickness of approximately 100-250 Angstroms.

US Patent:

20080268587, Oct 30, 2008

Filed:

Apr 30, 2007

Appl. No.:

11/742081

Inventors:

Mariam G. Sadaka - Austin TX, US
Debby Eades - Manor TX, US
Joe Mogab - Austin TX, US
Melissa O. Zavala - Leander TX, US
Gregory S. Spencer - Pflugerville TX, US

International Classification:

H01L 21/8238

US Classification:

438199, 257E21632

Abstract:

A semiconductor process and apparatus provide a high performance CMOS devices () with hybrid or dual substrates by etching a deposited oxide layer () using inverse slope isolation techniques to form tapered isolation regions () and expose underlying semiconductor layers () in a bulk wafer structure prior to epitaxially growing the first and second substrates () having different surface orientations that may be planarized with a single CMP process. By forming first gate electrodes (104) over a first substrate () that is formed by epitaxially growing (100) silicon and forming second gate electrodes () over a second substrate () that is formed by epitaxially growing (110) silicon, a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes having improved hole mobility.