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Davoud Safari

age ~66

from Georgetown, TX

Also known as:
  • Davoud Safaru
  • David Safari
  • Davoud Ds Safari
20324 Hunters Point Dr, Georgetown, TX 78628512 763-1063

Davoud Safari Phones & Addresses

  • 20324 Hunters Point Dr, Georgetown, TX 78628 • 512 763-1063
  • Lago Vista, TX
  • Travis, TX
  • Round Rock, TX
  • Atlanta, GA
  • 20324 Hunters Point Dr, Georgetown, TX 78633 • 512 470-9106

Work

  • Position:
    Food Preparation and Serving Related Occupations

Education

  • Degree:
    Graduate or professional degree

Us Patents

  • Method And Apparatus For Testing Gang Memory Modules

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  • US Patent:
    60556536, Apr 25, 2000
  • Filed:
    Apr 27, 1998
  • Appl. No.:
    9/067177
  • Inventors:
    Michael LeBlanc - Austin TX
    Davoud Safari - Round Rock TX
    Edwin Smith - Leander TX
  • Assignee:
    Compaq Computer Corporation - Houston TX
  • International Classification:
    G11C 2900
  • US Classification:
    714718
  • Abstract:
    The gangSIMM Memory Tester is a PWA which plugs directly into a CPU's SIMM slot. The gangSIMM Memory Tester contains a known good SIMM, which is connected directly to the CPU's bus. All memory functions for this SIMM slot is provided by the gold SIMM per normal SIMM operation. The CPU bus routed to the gold SIMM on the gangSIMM Memory Tester is also routed to a test bus via a buffer which provides increased drive capacity. The test bus is distributed in parallel to N number of SIMM slots located on the gangSIMM Memory Tester throughout a second set of tri-stating buffers. During read accesses to memory involving the CPUs SIMM slot location where the gangSIMM PWA is directly plugged into, data provided by the gold SIMM is compared on an individual basis with the data provided by an under-test SIMM. This operation occurs in-parallel for all under-test SIMMs.
  • Logic Analyzer Probe Assembly With Probe And Interface Boards

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  • US Patent:
    60922249, Jul 18, 2000
  • Filed:
    May 27, 1998
  • Appl. No.:
    9/086002
  • Inventors:
    Michael LeBlanc - Austin TX
    Davoud Safari - Round Rock TX
    Edwin Smith - Leander TX
  • Assignee:
    Compaq Computer Corporation - Houston TX
  • International Classification:
    G01R 3128
  • US Classification:
    714724
  • Abstract:
    The Logic Analyzer Probe Board is a hardware design which allows convenient access to signals on a printed circuit board. On one side of the Probe Board assembly is a collection of probes that provide contact to the printed-circuit boards pads, pins, vias and test points on the non-component side of a UUT. The other side of the Probe Board assembly contains an organized collection of connectors, or headers, that connect to a logic analyzer's cable harness. When the Probe Board mates with the printed circuit board, the Probe Board taps into a printed circuit board's signal via the probe-to-pad connection and routes the detected signal via one of the header pins to the logic analyzer. The design of the printed circuit board includes test points that correspond to each signal under test. Once the layout of a printed circuit board is determined, a custom-designed Probe Board may be designed that is cable of accessing each test point.
  • Cell Architecture For Built-In Self-Test Of Application Specific Integrated Circuits

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  • US Patent:
    55464068, Aug 13, 1996
  • Filed:
    Jul 26, 1995
  • Appl. No.:
    8/507737
  • Inventors:
    Russell L. Gillenwater - Round Rock TX
    Davoud Safari - Round Rock TX
    Gary D. Owens - Austin TX
  • Assignee:
    Tandem Computers, Inc. - Cupertino CA
  • International Classification:
    G01R 3128
    H04B 1700
  • US Classification:
    371 225
  • Abstract:
    An application specific integrated circuit (ASIC) includes ASIC logic, test logic, dual function input test cells and dual function output test cells. The test logic with the input and output test cells provides manufacturing test capability for the ASIC logic with a plurality of input pins and a plurality of output pins while reducing both the gate count and signal time delay associated with the input and output test cells. Each input test cell includes a boundary scan circuit means and a built-in self-test circuit means. An input test cell has a signal propagation time delay for a signal, that travels from an input pin to an ASIC logic input line, equivalent to one two-to-one multiplexer signal propagation delay. Hence, while the input test cell has the capability of both built-in self-test and boundary scan testing, the dual capability is achieved without incurring a signal propagation time delay for each capability. Like the input test cells, each output test cell includes a boundary scan circuit means and a built-in self-test circuit means.
  • Fail Safe, Fault Tolerant Circuit For Manufacturing Test Logic On Application Specific Integrated Circuits

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  • US Patent:
    54043590, Apr 4, 1995
  • Filed:
    Jun 29, 1992
  • Appl. No.:
    7/906196
  • Inventors:
    Russell L. Gillenwater - Round Rock TX
    Davoud Safari - Round Rock TX
    Gary D. Owens - Austin TX
  • Assignee:
    Tandem Computers Incorporated - Cupertino CA
  • International Classification:
    G01R 3128
    G06F 1560
  • US Classification:
    371 225
  • Abstract:
    An application specific integrated circuit (ASIC) includes ASIC logic and test logic that includes a fail-safe circuit and test logic circuitry. The test logic in conjunction with input and output test cells provides manufacturing test capability for the ASIC logic with a plurality of input pins and a plurality of output pins. The test logic generates several control signals that can affect operation of the ASIC logic. If any one of these signals is driven active by either a failure or a defect, the ASIC logic would be rendered inoperative. Consequently, each of these control signals is routed to the fail-safe circuit. These control signals include, for example, tri-state and reset signals and other control signals generated by test logic circuitry for the built-in testing of the ASIC. The fail-safe circuit generates a fail-safe control output signal for a corresponding control input signal from the test logic circuitry only during manufacturing testing when a fail-safe enable signal is applied to the fail-safe circuit. Preferably, the fail-safe enable signal is provided on one of the plurality of pins connected to the test logic so that the fail-safe enable signal cannot be generated by a failure or defect in the test logic circuitry.

Resumes

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Davoud Safari

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Location:
Austin, Texas Area
Industry:
Computer Networking
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Retired At No Company

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Position:
Retired at No Company
Location:
United States
Industry:
Accounting
Work:
No Company
Retired

Mylife

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Davoud Safari Georgetown...

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Classmates

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Davoud Safari

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Schools:
Prospect Elementary School Oberlin OH 1995-1999
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Prospect Elementary Schoo...

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Graduates:
Davoud Safari (1995-1999),
Candy Barr (1958-1962),
Anthony Hill Jr (1985-1988),
Toya Young (1992-1993)

Facebook

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Googleplus

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