David T Su

US Patent:

6404289, Jun 11, 2002

Filed:

Dec 22, 2000

Appl. No.:

09/747778

Inventors:

David K. Su - Mountain View CA
Chik Patrick Yue - Milpitas CA
David J. Weber - Sunnyvale CA
Masound Zargari - Mountain View CA

Assignee:

Atheros Communications, Inc. - Sunnyvale CA

International Classification:

H03L 7095

US Classification:

331 4, 331179, 331DIG 2, 327156

Abstract:

The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions, and a divide circuit implemented using only a single counter along with a decoder. This allows for a method of operating the synthesizer, methods of establishing or reestablishing a lock condition using the extended range VCO, and a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.

US Patent:

6483188, Nov 19, 2002

Filed:

May 15, 2000

Appl. No.:

09/571004

Inventors:

Chik Patrick Yue - Milpitas CA
Masoud Zargari - Mountain View CA
David Su - Mountain View CA

Assignee:

Atheros Communications, Inc. - Palo Alto CA

International Classification:

H01L 27095

US Classification:

257728, 257165, 257206, 257401, 257500, 257538, 257723, 257724, 257725, 257584, 257579, 257578, 257587

Abstract:

A radio-frequency (RF) integrated circuit is described. In one embodiment, the IC comprises multiple metal layers forming multiple transistors on a non-epitaxial substrate. The transistors are step and mirror symmetric. Also, the RF signal lines are on a top metal layer above all other metal layers and the power and ground planes are on a bottom metal layer below all other metal layers. The top and bottom metal layers are separated by a shield that extends beyond the RF signal lines by a distance that is at least the same distance that the shield is away from the RF lines. Low frequency signals are on signal lines below the top metal layer.

US Patent:

6504431, Jan 7, 2003

Filed:

Mar 26, 2002

Appl. No.:

10/109412

Inventors:

David J. Weber - Sunnyvale CA
Patrick Yue - Milpitas CA
David Su - Mountain View CA

Assignee:

Atheros Communications, Inc. - Sunnyvale CA

International Classification:

H03F 345

US Classification:

330253, 330297, 330310

Abstract:

The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator. This results in the first transconductance being greater than the second transconductance, and the second breakdown voltage being greater than the first breakdown voltage.

US Patent:

6504433, Jan 7, 2003

Filed:

Sep 15, 2000

Appl. No.:

09/663101

Inventors:

David J. Weber - Sunnyvale CA
Patrick Yue - Milpitas CA
David Su - Mountain View CA

Assignee:

Atheros Communications, Inc. - Sunnyvale CA

International Classification:

H03F 122

US Classification:

330277, 330311

Abstract:

The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator. This results in the first transconductance being greater than the second transconductance, and the second breakdown voltage being greater than the first breakdown voltage.

US Patent:

6509779, Jan 21, 2003

Filed:

Feb 7, 2002

Appl. No.:

10/072191

Inventors:

Chik Patrick Yue - Milpitas CA
David Kuochieh Su - Mountain View CA
William John McFarland - Los Altos CA

Assignee:

Atheros Communications, Inc. - Sunnyvale CA

International Classification:

H03K 508

US Classification:

327310, 327324, 327309, 361 917

Abstract:

An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.

US Patent:

6570453, May 27, 2003

Filed:

Mar 13, 2002

Appl. No.:

10/099229

Inventors:

David K. Su - Mountain View CA
Chik Patrick Yue - Milpitas CA
David J. Weber - Sunnyvale CA
Masound Zargari - Mountain View CA

Assignee:

Atheros Communications, Inc. - Sunnyvale CA

International Classification:

H03L 700

US Classification:

331 1A

Abstract:

The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions, and a divide circuit implemented using only a single counter along with a decoder. This allows for a method of operating the synthesizer, methods of establishing or reestablishing a lock condition using the extended range VCO, and a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.

US Patent:

6593794, Jul 15, 2003

Filed:

Feb 7, 2002

Appl. No.:

10/072132

Inventors:

Chik Patrick Yue - Milpitas CA
David Kuochieh Su - Mountain View CA
William John McFarland - Los Altos CA

Assignee:

Atheros Communications - Sunnyvale CA

International Classification:

H03K 508

US Classification:

327310, 327324, 327309, 361 917

Abstract:

An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.

US Patent:

6597227, Jul 22, 2003

Filed:

Jan 21, 2000

Appl. No.:

09/488940

Inventors:

Chik Patrick Yue - Milpitas CA
David Kuochieh Su - Mountain View CA
William John McFarland - Los Altos CA

Assignee:

Atheros Communications, Inc. - Sunnyvale CA

International Classification:

H02H 320

US Classification:

327310, 327311, 361 56, 361 911, 361 917

Abstract:

An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.