David M Purdham from Eden Prairie, MN, age 69

David Purdham

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David Purdham (b. June 3, 1951 in San Antonio, Texas) is an American character actor who stars in films and on television. Purdham's first role was in the 1984 film Lily in Love ...

Greater Minneapolis-St Paul Area

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Location:

Minneapolis, MN

Industry:

Computer Hardware

Work:

Marvell
Senior Staff Engineer
QLogic Apr 2001 - Nov 2005
Principal Engineer

Education:

University of Minnesota-Twin Cities 1976 - 1979
BSEE, Electrical Engineering

Skills:

Asic
Debugging
Soc
Semiconductors
Rtl Design
Ic
Field Programmable Gate Arrays
Verilog
Integrated Circuits
System on A Chip

David Purdham

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David Purdham

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Us Patents

Method And System For Embedded Disk Controllers
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US Patent:

7080188, Jul 18, 2006
Filed:

Mar 10, 2003
Appl. No.:

10/385022
Inventors:

Larry L. Byers - Apple Valley MN, US
Paul B. Ricci - Coto Fe Caza CA, US
Joseph G. Kriscunas - Dove Canyon CA, US
Joseba M. Desubijana - Minneapolis MN, US
Gary R. Robeck - Albertville MN, US
Michael R. Spaur - Dana Point CA, US
David M. Purdham - Brooklyn Park MN, US
Assignee:

Marvell International Ltd. - Hamilton
International Classification:

G06F 13/36
G06F 13/24
US Classification:

710306, 710260, 710264, 710313
Abstract:

A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface; an interrupt controller module that can generate a fast interrupt to the first main processor; a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.

Interrupt Controller For Processing Fast And Regular Interrupts
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US Patent:

7457903, Nov 25, 2008
Filed:

Mar 10, 2003
Appl. No.:

10/384991
Inventors:

David M. Purdham - Brooklyn Park MN, US
Larry L. Byers - Apple Valley MN, US
Andrew Artz - Saint Louis Park MN, US
Assignee:

Marvell International Ltd. - Hamilton
International Classification:

G06F 13/14
US Classification:

710269, 710 48, 710311
Abstract:

A method and system for generating interrupts in an embedded disk controller is provided. The method includes receiving vector values for an interrupt; determining if an interrupt request is pending; comparing the received vector value with a vector value of the pending interrupt; and replacing a previous vector value with the received vector value if the received vector value has higher priority. The system includes, at least one register for storing a trigger mode value which specifies whether an interrupt is edge triggered or level sensitive, and a vector address field that specifies a priority and address for an interrupt, and a mask value which masks an interrupt source. Also provided is a method for generating a fast interrupt. The method includes, receiving an input signal from a fast interrupt source; and generating a fast interrupt signal based on priority and a mask signal.

Interrupt Controller For Prioritizing Interrupt Requests In An Embedded Disk Controller
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US Patent:

7870320, Jan 11, 2011
Filed:

Nov 14, 2008
Appl. No.:

12/271261
Inventors:

David M. Purdham - Brooklyn Park MN, US
Larry L. Byers - Apple Valley MN, US
Andrew Artz - Saint Louis Park MN, US
Assignee:

Marvell International Ltd. - Hamilton
International Classification:

G06F 13/14
US Classification:

710269, 710 48, 710311
Abstract:

An interrupt controller for a disk controller includes an interrupt scanner module that receives a plurality of interrupt requests (IRQs) from a plurality of corresponding interrupt sources, performs a scan of respective vector values of the plurality of IRQs, and selectively outputs a priority based on the scan. An interrupt generation module receives the priority and generates at least one of a fast interrupt and a regular interrupt based on the priority.

Servo Controller Interface Module For Embedded Disk Controllers
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US Patent:

7870346, Jan 11, 2011
Filed:

Mar 9, 2004
Appl. No.:

10/796727
Inventors:

Larry L. Byers - Apple Valley MN, US
David M. Purdham - Brooklyn Park MN, US
Michael R. Spaur - Dana Point CA, US
Assignee:

Marvell International Ltd. - Hamilton
International Classification:

G06F 12/00
G06F 13/18
US Classification:

711150, 711112, 711152, 710244
Abstract:

An embedded disk controller (“controller”) having a servo controller is provided. The controller also includes a servo controller interface with a speed matching module and a pipeline control module such that at least two processors share memory mapped registers without conflicts. The processors operate at different frequencies, while the servo-controller and the servo controller interface operate in same or different frequency domains. The pipeline control module resolves conflict between the first and second processor transaction. The speed matching module ensures communication without inserting wait states in a servo controller interface clock domain for write access to the servo controller and there is no read conflicts between the first and second processor. The controller also includes a hardware mechanism for indivisible register acess to the first or second processor. The hardware mechanisim includes a hard semaphore and/or soft semaphore.

Memory Fault Injection
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US Patent:

8181100, May 15, 2012
Filed:

Jan 23, 2009
Appl. No.:

12/359159
Inventors:

David M. Purdham - Eden Prairie MN, US
Larry L. Byers - Apple Valley MN, US
Thomas F. Koehmstedt - Shakopee MN, US
Assignee:

Marvell International Ltd. - Hamilton
International Classification:

G06F 7/02
US Classification:

714819
Abstract:

Techniques, apparatus, and systems for injecting a memory fault can include obtaining first data and second data different from the first data, generating first error detection information based on the first data, writing the second data to a memory unit using a specified address, and using the first error detection information as error detection information for the second data to create a memory fault condition.

Method And System For Embedded Disk Controllers
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US Patent:

20060230214, Oct 12, 2006
Filed:

Jun 6, 2006
Appl. No.:

11/447572
Inventors:

Larry Byers - Apple Valley MN, US
Paul Ricci - Coto De Caza CA, US
Joseph Kriscunas - Dove Canyon CA, US
Joseba Desubijana - Minneapolis MN, US
Gary Robeck - Albertville MN, US
Michael Spaur - Dana Point CA, US
David Purdham - Brooklyn Park MN, US
Assignee:

Marvell International Ltd. - Hamilton
International Classification:

G06F 13/14
US Classification:

710305000
Abstract:

An embedded disk controller comprises a main processor in communication with a first bus. A second processor is in communication with a second bus. An external bus controller (EBC) is in communication with the first bus and in communication with external devices via an external bus interface. A history module is located in the embedded disk controller, communicates with the first bus and the second bus, and at least one of monitors transaction information of one of said external devices and masks information of one of said external devices via the EBC based on setup information, wherein the EBC and the history module are located on at least on of an integrated circuit (IC) and a system on a chip (SOC) with the embedded disk controller.

Unconditional Clock And Automatic Refresh Logic
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US Patent:

49531310, Aug 28, 1990
Filed:

Sep 7, 1988
Appl. No.:

7/241421
Inventors:

David M. Purdham - Brooklyn Park MN
James H. Scheuneman - St. Paul MN
Larry L. Byers - Apple Valley MN
Terence Sych - Minneapolis MN
Kwisook Tsang - Shoreview MN
Assignee:

Unisys Corporation - Blue Bell PA
International Classification:

G11C 700
US Classification:

365222
Abstract:

A novel unconditional clock and automatic refresh logic system is provided which comprises a source of unconditional clock pulses coupled to the memory control logic in a manner which permits automatic refreshing of a dynamic memory. There is further provided clock logic means which sense the conditions in the dynamic memory system during which the dynamic memory is not being refreshed. There is further provided, means for generating automatic clock refresh signals coupled to the memory control logic for initiating continuous automatic refresh cycles when the system clock is being shutdown.

Priority Logic For Selecting And Stacking Data
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US Patent:

59702532, Oct 19, 1999
Filed:

Jan 9, 1997
Appl. No.:

8/780966
Inventors:

David M. Purdham - Brooklyn Park MN
Assignee:

Unisys Corporation
International Classification:

G06F 1314
US Classification:

395732
Abstract:

A method and apparatus for setting a priority sequence among a plurality of requesters using a common destination within a computer system. An advantage is that all requesters contending for the common destination will have timely access with respect to all other competing requesters. In a first exemplary embodiment of the present invention, a priority controller can use a two-level priority scheme to select the next requester. The first level of priority alternates between an external requester and an on-card requester where every other set of data is from the external requester. The second level of priority alternates between on-card modules during an on-card priority cycle. In an alternative exemplary embodiment, the priority controller can stack a request to transfer acknowledge and data information from an external requester if it is busy. The priority controller also prevents sending an acknowledgment/data cycle out to an external source to prevent sending more data than the FIFO stacks can accommodate. The data may also consist only of acknowledgements.