David A Grosch

US Patent:

7400162, Jul 15, 2008

Filed:

Feb 20, 2003

Appl. No.:

10/539247

Inventors:

Anne Gattiker - Austin TX, US
David A. Grosch - Burlington VT, US
Marc D. Knox - Hinesburg VT, US
Franco Motika - Hopewell Junction NY, US
Phil Nigh - Williston VT, US
Jody Van Horn - Underhill VT, US
Paul S. Zuchowski - Jericho VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/26

US Classification:

324765, 3241581

Abstract:

Methods for testing a semiconductor circuit () including testing the circuit and modifying a well bias () of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control () of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

US Patent:

7486098, Feb 3, 2009

Filed:

Oct 22, 2007

Appl. No.:

11/876066

Inventors:

Anne Gattiker - Austin TX, US
David A. Grosch - Burlington VT, US
Marc D. Knox - Hinesburg VT, US
Franco Motika - Hopewell Junction NY, US
Phil Nigh - Williston VT, US
Jody Van Horn - Underhill VT, US
Paul S. Zuchowski - Jericho VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/26

US Classification:

324765, 3241581

Abstract:

A method for testing a semiconductor circuit () including testing the circuit and modifying a well bias () of the circuit during testing. The method improves the resolution of IDDQ testing and diagnosis by modifying well bias during testing. The method applies to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control () of the well potentials during test. In general, the method relies on using the well bias to change transistor threshold voltages.

US Patent:

7564256, Jul 21, 2009

Filed:

May 13, 2008

Appl. No.:

12/119834

Inventors:

Anne Gattiker - Austin TX, US
David A. Grosch - Burlington VT, US
Marc D. Knox - Hinesburg VT, US
Franco Motika - Hopewell Junction NY, US
Phil Nigh - Williston VT, US
Jody Van Horn - Underhill VT, US
Paul S. Zuchowski - Jericho VT, US

Assignee:

International Business Machines Company - Armonk NY

International Classification:

G01R 31/26

US Classification:

324765, 3241581

Abstract:

Methods for testing a semiconductor circuit () including testing the circuit and modifying a well bias () of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control () of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

US Patent:

7759960, Jul 20, 2010

Filed:

Apr 16, 2008

Appl. No.:

12/103906

Inventors:

Anne E. Gattiker - Austin TX, US
David A. Grosch - Burlington VT, US
Marc D. Knox - Hinesburg VT, US
Franco Motika - Hopewell Junction NY, US
Phil Nigh - Williston VT, US
Jody Van Horn - Underhill VT, US
Paul S. Zuchowski - Jericho VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/26

US Classification:

324765, 3241581

Abstract:

Methods for testing a semiconductor circuit () including testing the circuit and modifying a well bias () of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control () of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

US Patent:

20130069678, Mar 21, 2013

Filed:

Sep 20, 2011

Appl. No.:

13/236696

Inventors:

David Grosch - Burlington VT, US
Marc D. Knox - Hinesburg VT, US
Erik A. Nelson - Waterbury VT, US
Brian C. Noble - Lagrangeville NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G01R 31/30

US Classification:

32475002

Abstract:

Method and apparatus for margin testing integrated circuits. The method includes selecting a clock frequency, an operating temperature range and a power supply voltage level for margin testing an integrated circuit wherein one or more of the clock frequency, the operating temperature range and the power supply voltage level is outside of the normal operating conditions of the integrated circuit; applying an asynchronously time varying power supply voltage set to the selected power supply voltage level to the integrated circuit; running the integrated circuit chip at the selected clock frequency and maintaining the integrated circuit within the selected temperature range; applying a continuous test pattern to the integrated circuit; and monitoring the integrated circuit for fails.

US Patent:

61227609, Sep 19, 2000

Filed:

Aug 25, 1998

Appl. No.:

9/138997

Inventors:

David Alan Grosch - Burlington VT
Marc Douglas Knox - Hinesburg VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128

US Classification:

714724

Abstract:

An improved technique for testing semi-conductor chips having different types of circuits thereof is provided. The burn-in test includes providing test engines and/or externally applied patterns for each of the different types of circuits, stressing at high temperature and increased voltage, the semi-conductor containing both types of circuits, and running a sequence of patterns on each of said types of circuits simultaneously by the use of the engines for at least one of the types of circuits.