David Allan Beeson

US Patent:

8138826, Mar 20, 2012

Filed:

Jul 22, 2010

Appl. No.:

12/841847

Inventors:

Ansuya P. Bhatt - Cupertino CA, US
Raminder Jit Singh - San Jose CA, US
Adam Abed - Sunnyvale CA, US
David A. Beeson - Pleasanton CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03F 1/02

US Classification:

330 9, 330253, 330251, 330207 A

Abstract:

A circuit and method for signal amplification is provided. The circuit includes an amplifier including an input amplifier that is arranged to receive an input analog signal, and to provide an input amplifier output signal by amplifying the input analog signal. The amplifier further includes a DC offset correction circuit that is arranged to determine a DC offset correction for the input amplifier each time the amplifier is powered up. The DC offset correction is performed by iteratively adjusting a DC offset of the input amplifier until the input amplifier output DC offset is zero when the input analog AC signal is zero, within a predetermined tolerance. The DC offset correction circuit is further arranged to provide the determined DC offset correction to the input amplifier during operation of the amplifier.

US Patent:

20050058235, Mar 17, 2005

Filed:

Nov 6, 2003

Appl. No.:

10/605929

Inventors:

David Beeson - Pleasanton CA, US
Edward Chan - Fremont CA, US

International Classification:

H03D003/24

US Classification:

375376000

Abstract:

A clock recovery system () for recovering an input data signal () clock. A rate detector () detects the input data signal bit rate and provides range signals (-) specifying progressive ranges encompassing the bit rate. A frequency detector () provides a frequency error signal () based on frequency difference between the input data signal and a recovered clock signal (). A phase detector () provides a phase error signal () based on the input data and recovered clock signals. A filter-controller () provides an oscillator driving signal () based on the range, frequency error, and phase error signals. An oscillator-divider () then provides the recovered clock signal based on the oscillator driving signal and at least some of the range signals. The phase detector, filter-controller, and oscillator-divider collectively thus form a phase locked loop. Optionally, the clock recovery system () may also provide a recovered data signal ().

Author:

David Beeson

ISBN #:

0262111225

Author:

David Beeson

ISBN #:

0262610590