David M Arnesen

US Patent:

6381661, Apr 30, 2002

Filed:

May 28, 1999

Appl. No.:

09/321905

Inventors:

Shayne Messerly - Farmington UT
Harrison Killian - Kaysville UT
David Arnesen - West Jordan UT

Assignee:

3Com Corporation - Santa Clara CA

International Classification:

G06F 1312

US Classification:

710 63, 710 52, 710129

Abstract:

The high throughput UART to DSP interface (UDIF) maintains UART functionality while integrating dual Transmit (Tx) and Receive (Rx) FIFO buffers that are optimized for more efficient interaction with their respective I/O processors. The portion of the interface design interacting with the DSP, the UDIF, provides several unique Status, Informational, and Control registers that lower the DSP overhead required for many of the basic modem functions. The UDIF design also performs parity add, parity strip, and character echo functions, traditionally performed at a high overhead cost by the DSP. These functions are more efficiently preformed by hardware implementations than by the software routines executed by the DSP. More burdensome command functions like escape, AT, and flow control commands can also be implemented through hardware implementations to reduce processor overhead.

US Patent:

6438628, Aug 20, 2002

Filed:

May 28, 1999

Appl. No.:

09/322952

Inventors:

Shayne Messerly - Farmington UT
Harrison Killian - Kaysville UT
David Arnesen - West Jordan UT

Assignee:

3Com Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

710 35, 710 8, 710 59, 710262

Abstract:

The present invention increases data transfer rate and reduces interrupt latency while avoiding a concomitant increase in interrupts to the host, by pacing the data flow between the UART and DSP using burst modes and wait modes.

US Patent:

6557108, Apr 29, 2003

Filed:

May 28, 1999

Appl. No.:

09/322953

Inventors:

David Moore - Riverton UT
Harrison Killian - Kaysville UT
David Arnesen - West Jordan UT

Assignee:

3Com Corporation - Santa Clara CA

International Classification:

G06F 104

US Classification:

713500, 713 1, 713300, 713320, 713323, 709200, 709222

Abstract:

A system and method for providing a shortened DSP reset pulse to cause a modem to reset and enter a sleep mode as soon as possible after receipt of an external reset pulse issued by a host. A reset controller detects the external reset pulse, issues a separate reset pulse to the modem, monitors the modems clock and then terminates the separate reset pulse after a prescribed duration. The prescribed duration is determined by the minimum time required by the DSP to reset. The invention is embodied in a modem connected to an external controller. The modem includes a DSP having a reset terminal and a clock. The DSP begins performing a reset upon a first signal applied to its reset terminal and causes the modem to enter a sleep-mode after a second signal is applied to its reset terminal. The external controller is capable of transmitting an external signal. The reset controller in the modem has a counter and an output node.

US Patent:

7020218, Mar 28, 2006

Filed:

Jun 18, 2001

Appl. No.:

09/883834

Inventors:

David M. Arnesen - West Jordan UT, US

International Classification:

H04L 27/06
H04B 1/10

US Classification:

375316, 375350

Abstract:

A system for a sliding-window transform with integrated windowing is described. The system provides a Direct Fourier Transform kernel with an integrated windowing filter having a desired number of stages. In one embodiment, the windowing filter is a lowpass filter. In one embodiment, the lowpass filter has a rectangular filter transfer characteristic. The DFT includes a complex multiplier. A first portion of the windowing filter is provided before the complex multiplier and can be implemented using real arithmetic. A second portion of the windowing filter is provided after the complex multiplier and is implemented using complex arithmetic. In one embodiment, the filter weights of the second portion of the windowing filter are unity and thus no multiplier is needed for the filter weights in the second portion of the windowing filter.

US Patent:

6055245, Apr 25, 2000

Filed:

Mar 31, 1997

Appl. No.:

8/831459

Inventors:

Eric P. Mitchell - Ogden UT
Connie D. York - Riverton UT
Richard A. Kunz - Draper UT
Jeffrey A. Hanline - Bountiful UT
David M. Arnesen - West Jordan UT
Gerald A. Wilson - South Jordan UT

Assignee:

3COM Corporation - Santa Clara CA

International Classification:

H04J 102
H04J 312
H04M 300

US Classification:

370493

Abstract:

An apparatus and method for facilitating interaction during a communication session between an analog modem and a terminal adapter for conveying digital alert tones and control data therebetween is provided. The embodiments provide for a collateral digital communication path between a microcontroller of an analog modem and a microcontroller of a terminal adapter for selectively relaying digital alert tones and control data therebetween. One embodiment utilizes a cellular interface of an analog modem for tapping and evaluating information for the presence of control data. Upon successful identification of control data, the microcontroller of a terminal adapter is notified and the specific control data detected in identified. By providing a method of apparatus for digitally relaying control data, accuracy of identification of control data by a terminal adapter is enhanced by foregoing needless signal transformation and retransformation.

US Patent:

61283118, Oct 3, 2000

Filed:

Feb 26, 1998

Appl. No.:

9/031103

Inventors:

Spiro Poulis - Kearns UT
David M. Arnesen - West Jordan UT

Assignee:

3COM Corporation - Santa Clara CA

International Classification:

H04L 1266

US Classification:

370463

Abstract:

A method and apparatus for interconnecting via a serial bus a master processor and a co-processor having directly interfaceable parallel interfaces thereby accommodating the remote location of the co-processor from the master processor. The master processor interfaces with a serial bus interface for converting the parallel interface of the master processor into a serial interface forming a serial bus including a serial data out signal, a serial data in signal, a serial clock signal and a frame sync signal. The serial bus interfaces with the remote module having the co-processor located therein. The serial bus interfaces directly with an interface controller for converting the serial information back to a parallel format compatable with the requirements of the co-processor's parallel interface. The interface controller is further capable of generating control signals such as resets and general purpose outputs when directed by the master processor and reading status of the co-processor when also directed by the master processor. Testing functionality is also included for specific incorporation of an ISDN-specific I/O interface device functioning as the co-processor.

Address:

4123 W Shoshone Lk Dr, West Jordan, UT 84088

VIN:

2HKYF18637H514258

Make:

HONDA

Model:

PILOT

Year:

2007