Daniel J Hubbard

US Patent:

20230059543, Feb 23, 2023

Filed:

Aug 15, 2022

Appl. No.:

17/887940

Inventors:

- Boise ID, US
Dheeraj Srinivasan - San Jose CA, US
Ali Mohammadzadeh - Mountain View CA, US
Karl D. Schuh - Santa Cruz CA, US
Guido Luciano Rizzo - Avezzano, IT
Jung Sheng Hoei - Newark CA, US
Michele Piccardi - Cupertino CA, US
Tommaso Vali - Sezze, IT
Umberto Siciliani - Rubano, IT
Rohitkumar Makhija - Milpitas CA, US
June Lee - Sunnyvale CA, US
Aaron S. Yip - Los Gatos CA, US
Daniel J. Hubbard - Boise ID, US

International Classification:

G06F 3/06

Abstract:

A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.

US Patent:

20230043418, Feb 9, 2023

Filed:

Oct 29, 2021

Appl. No.:

17/514267

Inventors:

- Boise ID, US
Ali Mohammadzadeh - Mountain View CA, US
Dheeraj Srinivasan - San Jose CA, US
Daniel J. Hubbard - Boise ID, US
Luca Bert - San Jose CA, US

International Classification:

G06F 3/06

Abstract:

Exemplary methods, apparatuses, and systems include aggregating a plurality of memory status commands. Each command of the plurality of memory status commands is assigned a corresponding bit on a memory interface. The plurality of memory status commands are sent in parallel as an aggregate status command to one or more memory components via the memory interface.

US Patent:

20210342261, Nov 4, 2021

Filed:

Jul 13, 2021

Appl. No.:

17/374906

Inventors:

- Boise ID, US
Peter Feeley - Boise ID, US
Ashutosh Malshe - Fremont CA, US
Daniel J. Hubbard - Boise ID, US
Christopher S. Hale - Boise ID, US
Kevin R. Brandt - Boise ID, US
Sampath K. Ratnam - Boise ID, US
Yun Li - Fremont CA, US
Marc S. Hamilton - Eagle ID, US

International Classification:

G06F 12/02
G06F 12/0891
G06F 3/06
G06F 12/06
G06F 12/00

Abstract:

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

US Patent:

20210133099, May 6, 2021

Filed:

Jan 14, 2021

Appl. No.:

17/149349

Inventors:

- Boise ID, US
Sampath K. Ratnam - Boise ID, US
Peter Feeley - Boise ID, US
Michael G. Miller - Boise ID, US
Daniel J. Hubbard - Boise ID, US
Renato C. Padilla - Folsom CA, US
Ashutosh Malshe - Fremont CA, US
Harish R. Singidi - Santa Clara CA, US

International Classification:

G06F 12/02
G06F 3/06

Abstract:

An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.

US Patent:

20210073120, Mar 11, 2021

Filed:

Nov 16, 2020

Appl. No.:

17/099071

Inventors:

- Boise ID, US
Daniel J. Hubbard - Boise ID, US
Robert W. Strong - Folsom CA, US
Michael B. Danielson - Georgetown TX, US
Jonathan Tanguy - Boise ID, US

International Classification:

G06F 12/02
G06F 3/06

Abstract:

The present disclosure includes apparatuses and methods for directed sanitization of memory. One example method comprises, responsive to receiving a sanitization command, performing a deterministic garbage collection operation on a memory, wherein performing the deterministic garbage collection operation results in physical erasure of all invalid data stored on the memory without losing valid data stored on the memory.

US Patent:

20200183622, Jun 11, 2020

Filed:

Dec 7, 2018

Appl. No.:

16/213720

Inventors:

- Boise ID, US
Daniel J. Hubbard - Boise ID, US

International Classification:

G06F 3/06
G06F 12/02

Abstract:

Various embodiments described herein provide for a memory circuit package that comprises a plurality of memory die, a plurality of external memory channel interfaces, and a multiplexer circuit. The multiplexer circuit can selectively couple at least one memory die to either a first external memory interface (of the plurality of external memory channel interfaces) or a second external memory channel interface (of the plurality of external memory channel interfaces) based on a control input, thereby facilitating an adjustment in active memory channel count for the memory circuit package.

US Patent:

20200097402, Mar 26, 2020

Filed:

Nov 27, 2019

Appl. No.:

16/697724

Inventors:

- Boise ID, US
Peter Feeley - Boise ID, US
Ashutosh Malshe - Fremont CA, US
Daniel J. Hubbard - Boise ID, US
Christopher S. Hale - Boise ID, US
Kevin R. Brandt - Boise ID, US
Sampath K. Ratnam - Boise ID, US
Yun Li - Fremont CA, US
Marc S. Hamilton - Eagle ID, US

International Classification:

G06F 12/02
G06F 12/0891
G06F 3/06
G06F 12/06
G06F 12/00

Abstract:

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: select a garbage collection (GC) source block storing valid data, and designate a storage mode for an available memory block based on the valid data, wherein the storage mode is for configuring memory cells in the available memory block as cache memory that stores a number of bits less than maximum storage capacities thereof for subsequent or upcoming data writes.

US Patent:

20190303038, Oct 3, 2019

Filed:

Mar 27, 2018

Appl. No.:

15/937146

Inventors:

- Boise ID, US
Daniel J. Hubbard - Boise ID, US

International Classification:

G06F 3/06

Abstract:

Systems and methods for specifying storage media types in write commands executable by storage devices are disclosed. An example system comprises: a plurality of memory devices and a controller operatively coupled to the memory devices, the controller configured to: receive a write command specifying a data item and an identifier of a data stream comprising the data item; determine, by parsing the identifier of the data stream, a data stream attribute shared by data items comprised by the data stream; identify, based on the data stream attribute, a memory device managed by the controller; and transmit, to the memory device, an instruction specifying the data item.