Daniel Allen Hubbard

US Patent:

20230059543, Feb 23, 2023

Filed:

Aug 15, 2022

Appl. No.:

17/887940

Inventors:

- Boise ID, US
Dheeraj Srinivasan - San Jose CA, US
Ali Mohammadzadeh - Mountain View CA, US
Karl D. Schuh - Santa Cruz CA, US
Guido Luciano Rizzo - Avezzano, IT
Jung Sheng Hoei - Newark CA, US
Michele Piccardi - Cupertino CA, US
Tommaso Vali - Sezze, IT
Umberto Siciliani - Rubano, IT
Rohitkumar Makhija - Milpitas CA, US
June Lee - Sunnyvale CA, US
Aaron S. Yip - Los Gatos CA, US
Daniel J. Hubbard - Boise ID, US

International Classification:

G06F 3/06

Abstract:

A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.

US Patent:

20230043418, Feb 9, 2023

Filed:

Oct 29, 2021

Appl. No.:

17/514267

Inventors:

- Boise ID, US
Ali Mohammadzadeh - Mountain View CA, US
Dheeraj Srinivasan - San Jose CA, US
Daniel J. Hubbard - Boise ID, US
Luca Bert - San Jose CA, US

International Classification:

G06F 3/06

Abstract:

Exemplary methods, apparatuses, and systems include aggregating a plurality of memory status commands. Each command of the plurality of memory status commands is assigned a corresponding bit on a memory interface. The plurality of memory status commands are sent in parallel as an aggregate status command to one or more memory components via the memory interface.

US Patent:

20190065365, Feb 28, 2019

Filed:

Aug 31, 2017

Appl. No.:

15/693153

Inventors:

- Boise ID, US
Kishore Kumar Muchherla - Fremont CA, US
Peter Feeley - Boise ID, US
Ashutosh Malshe - Fremont CA, US
Daniel J. Hubbard - Boise ID, US
Christopher S. Hale - Boise ID, US
Kevin R. Brandt - Boise ID, US
Sampath K. Ratnam - Boise ID, US

International Classification:

G06F 12/02
G06F 12/0891

Abstract:

A memory system includes: a memory array including a plurality of memory cells, the plurality of memory cells including a plurality of cache memory cells; and a controller coupled to the memory array, the controller configured to: track usage of a first subset of the plurality of cache memory cells operating in a single-level cell (SLC) mode, wherein the tracking includes monitoring for an idle time event; and designate a storage mode for a second subset of the plurality of cache memory cells based on the tracked usage of the first subset, wherein the storage mode determines a storage density to be used for data writes.

US Patent:

20190065367, Feb 28, 2019

Filed:

Oct 22, 2018

Appl. No.:

16/167345

Inventors:

- Boise ID, US
Kishore Kumar Muchherla - Fremont CA, US
Peter Feeley - Boise ID, US
Ashutosh Malshe - Fremont CA, US
Daniel J. Hubbard - Boise ID, US
Christopher S. Hale - Boise ID, US
Kevin R. Brandt - Boise ID, US
Sampath K. Ratnam - Boise ID, US

International Classification:

G06F 12/02
G06F 12/0891

Abstract:

A memory system includes: a memory array including a plurality of memory cells, the plurality of memory cells including a plurality of cache memory cells; and a controller coupled to the memory array, the controller configured to: track usage of a first subset of the plurality of cache memory cells operating in a single-level cell (SLC) mode, wherein the tracking includes monitoring for an idle time event; and designate a storage mode for a second subset of the plurality of cache memory cells based on the tracked usage of the first subset, wherein the storage mode determines a storage density to be used for data writes.