Dana A Gryger

US Patent:

54468442, Aug 29, 1995

Filed:

Aug 5, 1991

Appl. No.:

7/741963

Inventors:

Thomas M. Steckler - Christiana PA
Dana A. Gryger - Downingtown PA
Robert H. Tickner - Paoli PA

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 1316

US Classification:

395250

Abstract:

An interface controller coupled between the main memory system and the I/O system of a large data processing system which controller is able to receive memory access requests from a number of different peripheral devices. The memory interface controller is provided with a data array for holding a number of data words fetched from memory which data array in turn is addressed by the output of an address array. The address array is an associative memory that can associate a given main memory address, of data in the data array, with a data array address containing data stored in main memory at that main memory address so that actual main memory access need not be required.

US Patent:

43778631, Mar 22, 1983

Filed:

Sep 8, 1980

Appl. No.:

6/184661

Inventors:

John E. Legory - Paoli PA
Dana A. Gryger - Downingtown PA
Daniel P. Drogichen - West Chester PA

Assignee:

Burroughs Corporation - Detroit MI

International Classification:

G06F 1110

US Classification:

371 42

Abstract:

In a data processing system wherein a binary data message is protected by cyclic check codes, synchronization loss tolerance is incorporated by performing a binary transformation after encoding the message but prior to transmitting it or writing it to storage and by performing an inverse binary transformation upon receiving it or reading it from storage but prior to error checking. In one embodiment the transformation involves complementing a plurality of bits. In an alternate embodiment the transformation involves reversing the sequence of a plurality of contiguous bits.

US Patent:

44159846, Nov 15, 1983

Filed:

Jun 25, 1980

Appl. No.:

6/162806

Inventors:

Dana A. Gryger - Downingtown PA
Daniel P. Drogichen - West Chester PA

Assignee:

Burroughs Corporation - Detroit MI

International Classification:

G06F 728
G06F 506

US Classification:

364900

Abstract:

Disclosed is a synchronous clock regenerator for generating a clock signal which can be reliably used to strobe a binary serial data signal. The incoming raw clock signal is fed into a tapped delay line which generates multiple delayed versions of the raw clock signal. Upon detection of a framing transition on the incoming data signal, the raw clock signal and multiple delayed clock signals are latched. The latched values are used to address a read only memory (ROM), the ROM containing codes specifying which, if any, of the set including the raw clock signal and multiple delayed clock signals provides the optimum phase to strobe the incoming data signal. The code read from the ROM is decoded, latched and fed to a l-of-n selector circuit. Thereafter, and until the next framing transition occurs, each raw clock pulse received is replaced by the corresponding one of the set of that raw clock pulse and the generated delayed versions of that raw clock pulse as selected by the previously latched inputs to the l-of-n selector.