Daisuke Hashimoto

US Patent:

20130134148, May 30, 2013

Filed:

Nov 2, 2012

Appl. No.:

13/667512

Inventors:

NHK Spring Co., Ltd. - Yokohama-shi, JP
Junichi Miyahara - Isehara-city, JP
Kazuhiro Yonekura - Isehara-city, JP
Toshihiko Hanamachi - Isehara-city, JP
Go Takahara - Isehara-city, JP
Jun Futakuchiya - Isehara-city, JP
Daisuke Hashimoto - Santa Clara CA, US

Assignee:

NHK Spring Co., Ltd. - Yokohama-shi

International Classification:

H01L 21/683
H05B 3/68

US Classification:

2194441

Abstract:

A substrate support device formed of a metal and having a high withstand voltage and a high thermal resistance is provided. A substrate support device according to the present invention includes a plate section formed of a metal; a shaft section connected to the plate section and formed of a metal; a heating element provided in the plate section; and an insulating film formed on a first surface of the plate section, the first surface opposite to the shaft section, by ceramic thermal spraying. The substrate support device may further include an insulating film formed on a second surface of the plate section which intersects the first surface of the plate section approximately perpendicularly.

US Patent:

20210303460, Sep 30, 2021

Filed:

Jun 14, 2021

Appl. No.:

17/346605

Inventors:

- Tokyo, JP
Daisuke HASHIMOTO - Cupertino CA, US

International Classification:

G06F 12/02
G06F 3/06

Abstract:

A storage system includes a host including a processor and a memory unit, and a storage device including a controller and a non-volatile memory unit. The processor is configured to output a write command, write data, and size information of the write data, to the storage device, the write command that is output not including a write address. The controller is configured to determine a physical write location of the non-volatile memory unit in which the write data are to be written, based on the write command and the size information, write the write data in the physical write location of the non-volatile memory unit, and output the physical write location to the host. The processor is further configured generate, in the memory unit, mapping information between an identifier of the write data and the physical write location.

US Patent:

20200341655, Oct 29, 2020

Filed:

Jul 9, 2020

Appl. No.:

16/925258

Inventors:

- Tokyo, JP
Daisuke HASHIMOTO - Cupertino CA, US

International Classification:

G06F 3/06
G06F 12/02
G06F 11/10
G11C 29/52
G11C 5/14
G06F 1/26

Abstract:

A memory system includes a memory device including a controller, a nonvolatile memory including physical blocks, a physical block being a unit of data erasure, and a volatile memory that stores block mapping data that maps each physical block to a free or an active physical block and indicates an erase count thereof. The memory system further includes a host device configured to receive the block mapping data from the memory device, compare a first erase count of a free physical block with a second erase count of an active physical block and determine whether a predetermined condition is met, and upon determining that the predetermined condition is met, cause the controller to copy data in the active physical block to the free physical block, and cause the controller to update the block mapping data to remap the active and free physical blocks to free and active physical blocks, respectively.

US Patent:

20200218451, Jul 9, 2020

Filed:

Mar 19, 2020

Appl. No.:

16/824203

Inventors:

- Tokyo, JP
Daisuke HASHIMOTO - Cupertino CA, US

International Classification:

G06F 3/06
G06F 12/02

Abstract:

A storage device includes a nonvolatile semiconductor memory device, and a controller configured to access the nonvolatile semiconductor memory device. When the controller receives a write command including a logical address, the controller determines a physical location of the memory device in which data are written and stores a mapping from the logical address to the physical location. When the controller receives a write command without a logical address, the controller determines a physical location of the memory device in which data are written and returns the physical location.

US Patent:

20200053154, Feb 13, 2020

Filed:

Oct 17, 2019

Appl. No.:

16/656411

Inventors:

- Tokyo, JP
Daisuke HASHIMOTO - Cupertino CA, US

International Classification:

H04L 29/08
G06F 3/06
G06F 12/02

Abstract:

A distributed system includes a plurality of storage systems and a network connecting the storage systems. Each storage system includes a host having a processor and a memory, and a storage device having a controller and a nonvolatile memory. When a first storage system receives, a second storage system, a write command, write data, and size information of the write data, the controller in the first storage system determines an address of the nonvolatile memory of the first storage system in which the write data are to be written, based on the write command and the size information, writes the write data in the nonvolatile memory associated with the address, and transmits the address to the second storage system, and the processor of the second storage system stores management data indicating correspondence between identification information of the write data and the address in the memory of the second storage system.

US Patent:

20200034287, Jan 30, 2020

Filed:

Sep 30, 2019

Appl. No.:

16/588438

Inventors:

- Tokyo, JP
Daisuke HASHIMOTO - Cupertino CA, US

International Classification:

G06F 12/02
G06F 3/06

Abstract:

A storage system includes a host including a processor and a memory unit, and a storage device including a controller and a non-volatile memory unit. The processor is configured to output a write command, write data, and size information of the write data, to the storage device, the write command that is output not including a write address. The controller is configured to determine a physical write location of the non-volatile memory unit in which the write data are to be written, based on the write command and the size information, write the write data in the physical write location of the non-volatile memory unit, and output the physical write location to the host. The processor is further configured generate, in the memory unit, mapping information between an identifier of the write data and the physical write location.

US Patent:

20200026644, Jan 23, 2020

Filed:

Sep 27, 2019

Appl. No.:

16/586517

Inventors:

- Tokyo, JP
Daisuke HASHIMOTO - Cupertino CA, US

International Classification:

G06F 12/02
G11C 29/00

Abstract:

A solid-state drive (SSD) is configured for dynamic resizing. When the SSD approaches the end of its useful life because the over-provisioning amount is nearing the minimum threshold as a result of an increasing number of bad blocks, the SSD is reformatted with a reduced logical capacity so that the over-provisioning amount may be maintained above the minimum threshold.

US Patent:

20200007623, Jan 2, 2020

Filed:

Sep 9, 2019

Appl. No.:

16/565320

Inventors:

- Tokyo, JP
Daisuke HASHIMOTO - Cupertino CA, US

International Classification:

H04L 29/08

Abstract:

A storage array includes a first controller, memory, and one or more storage devices. Each of the storage devices comprises a second controller and a nonvolatile memory. The first controller receives a command and data from a host connected to the storage array and transmits a response or data to the host. When a write command, write data, and size information of the write data are received from the host, the first controller sends the received data to the second controller. The second controller determines a write address indicating a memory region of the nonvolatile memory in which the write data are to be written, based on the write command and the size information, writes the write data in the memory region associated with the write address, and transmits the write address to the first controller. The first controller further transfers the write address to the host.