Cyrus Afghahi

US Patent:

6574136, Jun 3, 2003

Filed:

Nov 20, 2001

Appl. No.:

09/989595

Inventors:

Cyrus Afghahi - Mission Viejo CA
Sami Issa - Phoenix AZ
Zeynep Toros - Irvine CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 11401

US Classification:

365149, 365 63, 365 72

Abstract:

A random access memory cell ( ) includes a first conductor line ( ) and a second conductor line ( ). A native device ( ) is arranged to store charge. A high voltage threshold transistor ( ) couples the native device to the first and second conductors.

US Patent:

6600677, Jul 29, 2003

Filed:

Oct 19, 2001

Appl. No.:

10/037599

Inventors:

Cyrus Afghahi - Mission Viejo CA
Sami Issa - Phoenix AZ

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 1134

US Classification:

365187, 365222, 36518904

Abstract:

A system-on-chip (SOC) device or a random access memory (RAM) chip includes a RAM block. The RAM block includes memory cells, each of which has three transistors. Each memory cell is coupled to both a read bit line and a write bit line. A transparent continuous refresh mechanism has been implemented to read the content of a memory cell and re-write it back to the memory cell without disturbing the access (read/write) cycle, making refresh operations transparent to the system level. The continuous refresh mechanism includes a collision detection mechanism to prevent writing and reading the same memory cell at the same time.

US Patent:

6714467, Mar 30, 2004

Filed:

Jun 21, 2002

Appl. No.:

10/176843

Inventors:

Esin Terzioglu - Aliso Viejo CA
Gil I. Winograd - Aliso Viejo CA
Cyrus Afghahi - Mission Viejo CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 700

US Classification:

365200, 36523008

Abstract:

The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i. e. , replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.

US Patent:

6717863, Apr 6, 2004

Filed:

Apr 16, 2003

Appl. No.:

10/414878

Inventors:

Cyrus Afghahi - Mission Viejo CA
Sami Issa - Phoenix AZ

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 700

US Classification:

36518904, 365222

Abstract:

A system-on-chip (SOC) device or a random access memory (RAM) chip includes a RAM block. The RAM block includes memory cells, each of which has three transistors. Each memory cell is coupled to both a read bit line and a write bit line. A transparent continuous refresh mechanism has been implemented to read the content of a memory cell and re-write it back to the memory cell without disturbing the access (read/write) cycle, making refresh operations transparent to the system level. The continuous refresh mechanism includes a collision detection mechanism to prevent writing and reading the same memory cell at the same time.

US Patent:

6760243, Jul 6, 2004

Filed:

Jun 21, 2002

Appl. No.:

10/177001

Inventors:

Gil I. Winograd - Aliso Viejo CA
Esin Terzioglu - Aliso Viejo CA
Cyrus Afghahi - Mission Viejo CA
Ali Anvar - Irvine CA
Sami Issa - Phoenix AZ

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 502

US Classification:

365 63, 365 51

Abstract:

The present invention relates to a system and method for providing distributed, highly configurable modular predecoding. The system includes a hierarchical memory structure, including a predecoder adapted to perform a first layer of address predecoding and at least one local predecoder interacting with the global predecoder and adapted to perform a second layer of address predecoding.

US Patent:

6888761, May 3, 2005

Filed:

Jan 27, 2004

Appl. No.:

10/765535

Inventors:

Cyrus Afghahi - Mission Viejo CA, US
Sami Issa - Phoenix AZ, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C007/00

US Classification:

36518904, 36518907, 365222

Abstract:

A system-on-chip (SOC) device or a random access memory (RAM) chip includes a RAM block. The RAM block includes memory cells, each of which has three transistors. Each memory cell is coupled to both a read bit line and a write bit line. A transparent continuous refresh mechanism has been implemented to read the content of a memory cell and re-write it back to the memory cell without disturbing the access (read/write) cycle, making refresh operations transparent to the system level. The continuous refresh mechanism includes a collision detection mechanism to prevent writing and reading the same memory cell at the same time.

US Patent:

6898145, May 24, 2005

Filed:

May 10, 2004

Appl. No.:

10/842160

Inventors:

Gil I. Winograd - Aliso Viejo CA, US
Esin Terzioglu - Aliso Viejo CA, US
Cyrus Afghahi - Mission Viejo CA, US
Ali Anvar - Irvine CA, US
Sami Issa - Phoenix AZ, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C008/00

US Classification:

36523006, 365 63, 36523003

Abstract:

The present invention relates to a system and method for providing distributed, highly configurable modular predecoding. The method comprising forming a hierarchical memory structure including forming a first portion of the hierarchical memory structure adapted to perform a first layer of address predecoding. The method further comprises forming a second portion of the hierarchical memo structure interacting with at least the first portion and adapted to perform a second layer of address predecoding.

US Patent:

7177225, Feb 13, 2007

Filed:

Dec 5, 2003

Appl. No.:

10/729405

Inventors:

Esin Terzioglu - Aliso Viejo CA, US
Gil I. Winograd - Aliso Viejo CA, US
Cyrus Afghahi - Mission Viejo CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 11/00

US Classification:

36523006, 365200, 365239, 365240, 36523003

Abstract:

The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i. e. , replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one redundant predecoder adapted to be shifted in for at least one active predecoder of a plurality of predecoders adapted to be shifted out.