Craig A Eaton

US Patent:

7913103, Mar 22, 2011

Filed:

Aug 31, 2007

Appl. No.:

11/841179

Inventors:

Spencer M. Gold - Pepperell MA, US
Bill K. C. Kwan - Austin TX, US
Craig D. Eaton - Austin TX, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

G06K 1/00
H03K 3/017

US Classification:

713501, 713322, 327175

Abstract:

A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of a plurality of clock divider units which each divide the received reference clock signal to produce a corresponding divided clock signal. The method then removes one or more clock cycles (per a given number of cycles) in order to produce a plurality of domain clock signals each having an effective frequency based on a frequency and a number of cycles removed from the correspondingly received divided clock signal.