Corey V Swenson

US Patent:

7865854, Jan 4, 2011

Filed:

Apr 23, 2008

Appl. No.:

12/108145

Inventors:

Duane A. Averill - Rochester MN, US
Christopher T. Phan - Rochester MN, US
Corey V. Swenson - Rochester MN, US
Sharon D. Vincent - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716 5, 716 4, 716 6, 716 18, 703 13, 703 14, 710 5, 710 6, 710 7, 710 20, 710 21, 710 58, 710 59, 710 60, 710 61, 710260, 710261, 710262, 710263, 714724, 714728, 714738, 714739, 714740, 714741

Abstract:

A method for allowing simultaneous parameter-driven and deterministic simulation during verification of a hardware design, comprising: enabling a plurality of random parameter-driven commands from a random command generator to execute in a simulation environment during verification of the hardware design through a command managing device; and enabling a plurality of deterministic commands from a manually-driven testcase port to execute in the simulation environment simultaneously with the plurality of random parameter-driven commands during verification of the hardware design through the command managing device, the plurality of deterministic commands and the plurality of random parameter-driven commands each verify the functionality of the hardware design.

US Patent:

8494833, Jul 23, 2013

Filed:

May 9, 2008

Appl. No.:

12/118059

Inventors:

Eric O. Mejdrich - Rochester MN, US
Paul E. Schardt - Rochester MN, US
Corey V. Swenson - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/455
G06F 9/45

US Classification:

703 23, 703 22

Abstract:

Emulating a computer run time environment including: storing translated code in blocks of a translated code cache, each block of the translated code cache designated for storage of translated code for a separate one of the target executable processes, including identifying each block in dependence upon an identifier of the process for which the block is designated as storage; executing by the emulation environment a particular one of the target executable processes, using for target code translation the translated code in the block of the translated code cache designated as storage for the particular process; and upon encountering a context switch by the target operating system to execution of a new target executable process, changing from the block designated for the particular process to using for target code translation the translated code in the block of the translated code cache designated as storage for the new target executable process.

US Patent:

20050137841, Jun 23, 2005

Filed:

Dec 18, 2003

Appl. No.:

10/740326

Inventors:

Kevin Cook - Apple Valley MN, US
Corey Swenson - Rochester MN, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G06F017/50
G06F011/00

US Classification:

703014000, 714030000

Abstract:

A method, apparatus, system, and signal-bearing medium that in an embodiment generate keys based on a number of commands that can be outstanding at a device under test at any one time, embed the keys into respective data associated with respective commands, and send the commands to a device under test. When output is received from the device under test, the key embedded in the output may be used to determine the command associated with the output. In this way, the data may remain random while the test case command associated with the output may be determined based on the data.

US Patent:

20070005852, Jan 4, 2007

Filed:

Jun 30, 2005

Appl. No.:

11/173286

Inventors:

Thomas Armstead - Rochester MN, US
Eldon Nelson - Rochester MN, US
Paul Schardt - Rochester MN, US
Corey Swenson - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/00

US Classification:

710100000

Abstract:

Methods, apparatus, and articles of manufacture that allow packet-based communication transactions between devices over an interconnect bus to be captured in a standardized format are provided. The standardized format may enable the display of the bus transactions via a graphical user interface (GUI), which may greatly facilitate viewing and analyzing the transactions when validating communications.

US Patent:

20090271172, Oct 29, 2009

Filed:

Apr 24, 2008

Appl. No.:

12/108770

Inventors:

Eric O. Mejdrich - Rochester MN, US
Paul E. Schardt - Rochester MN, US
Corey V. Swenson - Rochester MN, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G06F 9/455

US Classification:

703 26

Abstract:

Emulating a computer run time environment as a component of a dynamic binary translation loop that translates target executable code compiled for execution on a target computer to code executable on a host computer of a kind other than the target computer, the target executable code including function calls to functions to be translated. Embodiments of the present invention include: determining, upon encountering in the binary translation loop a function call to a function to be translated, that the function call is a call to a host library function in a host native library; hashing a target executable image of the function to be translated from the target executable code, thereby producing a hash value; and using the hash value as an index to retrieve from a thunk table a host native address of the host library function in the host native library.

US Patent:

20130185542, Jul 18, 2013

Filed:

Jan 18, 2012

Appl. No.:

13/352907

Inventors:

Eric O. Mejdrich - Preston WA, US
Paul E. Schardt - Rochester MN, US
Robert A. Shearer - Rochester MN, US
Corey V. Swenson - Rochester MN, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 9/30

US Classification:

712214, 712E09016

Abstract:

An external Auxiliary Execution Unit (AXU) interface is provided between a processing core disposed in a first programmable chip and an off-chip AXU disposed in a second programmable chip to integrate the AXU with an issue unit, a fixed point execution unit, and optionally other functional units in the processing core. The external AXU interface enables the issue unit to issue instructions to the AXU in much the same manner as the issue unit would be able to issue instructions to an AXU that was disposed on the same chip. By doing so, the AXU on the second programmable chip can be designed, tested and verified independent of the processing core on the first programmable chip, thereby enabling a common processing core, which has been designed, tested, and verified, to be used in connection with multiple different AXU designs.