Chu-Chung Lee

US Patent:

6933614, Aug 23, 2005

Filed:

Sep 15, 2003

Appl. No.:

10/662541

Inventors:

Chu-Chung Lee - Round Rock TX, US
Fuaida Harun - Selangor, MY
Kevin J. Hess - Austin TX, US
Lan Chu Tan - Selangor, MY
Cheng Choi Yong - Selangor, MY

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L023/48

US Classification:

257780, 257781, 257750, 257758, 257775

Abstract:

An integrated circuit die () has a copper contact (), which, upon exposure to the ambient air, forms a native copper oxide. An organic material is applied to the copper contact which reacts with the native copper oxide to form an organic coating () on the copper contact in order to prevent further copper oxidation. In this manner, further processing at higher temperatures, such as those greater than 100 degrees Celsius, is not inhibited by excessive copper oxidation. For example, due to the organic coating, the high temperature of the wire bond process does not result in excessive oxidation which would prevent reliable wire bonding. Thus, the formation of the organic coating allows for a reliable and thermal resistance wire bond (). Alternatively, the organic coating can be formed over exposed copper at any time during the formation of the integrated circuit die to prevent or limit the formation of copper oxidation.

US Patent:

6937047, Aug 30, 2005

Filed:

Aug 5, 2003

Appl. No.:

10/634484

Inventors:

Tu-Anh Tran - Austin TX, US
Richard K. Eguchi - Austin TX, US
Peter R. Harper - Round Rock TX, US
Chu-Chung Lee - Round Rock TX, US
William M. Williams - Gilbert AZ, US
Lois Yong - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G01R031/02

US Classification:

324763, 324765

Abstract:

A semiconductor device has a large number of bond pads on the periphery for wirebonding. The semiconductor device has a module as well as other circuitry, but the module takes significantly longer to test than the other circuitry. A relatively small number of the bond pads, the module bond pads, are required for the module testing due, at least in part, to the semiconductor device having a built-in self-test (BIST) circuitry. The functionality of these module bond pads is duplicated on the top surface of and in the interior of the semiconductor device with module test pads that are significantly larger than the bond pads on the periphery. Having large pads for testing allows longer probe needles, thus increasing parallel testing capability. Duplicating the functionality is achieved through a test pad interface so that the module bond pads and the module test pads do not have to be shorted together.

US Patent:

6992377, Jan 31, 2006

Filed:

Feb 26, 2004

Appl. No.:

10/787288

Inventors:

Yaping Zhou - Austin TX, US
Chu-Chung Lee - Round Rock TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/48
H01L 23/52

US Classification:

257692, 257690, 438123

Abstract:

A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.

US Patent:

7049694, May 23, 2006

Filed:

Nov 9, 2005

Appl. No.:

11/270300

Inventors:

Yaping Zhou - Austin TX, US
Chu-Chung Lee - Round Rock TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/48
H01L 23/52

US Classification:

257692, 257690, 438123

Abstract:

A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.

US Patent:

7256488, Aug 14, 2007

Filed:

Mar 24, 2006

Appl. No.:

11/388646

Inventors:

Yaping Zhou - Austin TX, US
Chu-Chung Lee - Round Rock TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/48
H01L 23/52

US Classification:

257690, 257692, 257784, 257786, 438123

Abstract:

A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.

US Patent:

7355289, Apr 8, 2008

Filed:

Jul 29, 2005

Appl. No.:

11/192525

Inventors:

Kevin J. Hess - Austin TX, US
Chu-Chung Lee - Round Rock TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/28

US Classification:

257787, 257796

Abstract:

A semiconductor package () uses a plurality of thermal conductors (-) that extend upward within an encapsulant () from one or more thermal bond pads () on a die () to disperse heat. The thermal conductors may be bond wires or conductive stud bumps and do not extend beyond a lateral edge of the die. One or more of the thermal conductors may be looped within the encapsulant and exposed at an upper surface of the encapsulant. In one form a heat spreader () is placed overlying the encapsulant for further heat removal. In another form the heat spreader functions as a power or ground terminal directly to points interior to the die via the thermal conductors. Active bond pads may be placed exclusively along the die's periphery or also included within the interior of the die.

US Patent:

7374971, May 20, 2008

Filed:

Apr 20, 2005

Appl. No.:

11/110283

Inventors:

Yuan Yuan - Austin TX, US
Kevin J. Hess - Austin TX, US
Chu-Chung Lee - Round Rock TX, US
Tu-Anh Tran - Austin TX, US
Donna Woosley, legal representative - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/00

US Classification:

438113, 438114

Abstract:

An integrated circuit has a semiconductor substrate and an interconnect layer that mechanically relatively weak and susceptible to cracks and delamination. In the formation of the integrated circuit from a semiconductor wafer, a cut is made through the interconnect layer to form an edge of the interconnect layer. This cut may continue completely through the wafer thickness or stop short of doing so. In either case, after cutting through the interconnect layer, a reconditioning layer is formed on the edge of the interconnect layer. This reconditioning layer seals the existing cracks and delaminations and inhibits the further delamination or cracking of the interconnect layer. The sealing layer may be formed, for example, before the cut through the wafer, after the cut through the wafer but before any packaging, or after performing wirebonding between the interconnect layer and an integrated circuit package.

US Patent:

7550318, Jun 23, 2009

Filed:

Aug 11, 2006

Appl. No.:

11/502679

Inventors:

Kevin J. Hess - St. Ismier, FR
Chu-Chung Lee - Round Rock TX, US
James W. Miller - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/00
H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

438119, 257783, 257E21514, 257E23018

Abstract:

A method is provided for forming peripheral contacts between a die and a substrate. In accordance with the method, a die () is provided which has first and second opposing major surfaces, wherein the first major surface is attached to a substrate () having a first group () of contact pads disposed thereon, and wherein the second major surface has a second group () of contact pads disposed thereon. An electrically conductive pathway () is formed between the first and second groups of contacts with an electrically conductive polymeric composition.