Christopher M Tumas

US Patent:

6938112, Aug 30, 2005

Filed:

Dec 21, 2000

Appl. No.:

09/745919

Inventors:

Thomas R. Bayerl - Williamston MI, US
Christopher M. Tumas - Brooklyn MI, US

Assignee:

Sprint Communications Company L.P. - Overland Park KS

International Classification:

G06F013/00
H04L005/16

US Classification:

710107, 375219

Abstract:

The present invention discloses a method and apparatus for preventing contention on a common data bus between a CPU and a peripheral device with which the CPU exchanges data. A transceiver with bus hold is used to connect the bus connections of the CPU and peripheral. Control logic receives a CPU data strobe signal and generates control signals for the transceiver and the peripheral. After these control signals go inactive, the peripheral outputs transition to the high impedance state and the bus hold circuits maintain the last peripheral output data valid for reading by the CPU at the end of its read cycle. As soon as the CPU goes to a write cycle and drives the data bus, the bus hold circuits automatically switch to follow the new data.

US Patent:

6850535, Feb 1, 2005

Filed:

Nov 9, 2000

Appl. No.:

09/711113

Inventors:

Earl Goodrich, II - Lansing MI, US
Christopher M. Tumas - Brooklyn MI, US

Assignee:

Sprint Communications Company L.P. - Overland Park KS

International Classification:

H04L 1228

US Classification:

370419, 370401

Abstract:

The present invention discloses a system for buffering the outputs of peripheral devices operating in UTOPIA protocol to allow devices on separate circuit boards connected through long buses, such as backplanes, to communicate with the system controller. Address detection logic stores the peripheral device address and compares it to the UTOPIA bus address signal. When the correct address is recognized in a first clock cycle, a flip flop stores the information for the next cycle. A second flip flop stores the state of the read enable signal. An AND gate detects when the correct address was found and the read enable was de-asserted during the first clock cycle and the read enable and read cell available signals are positive during the current clock cycle and provides a high signal to a third flip flop. On a third clock cycle the third flip flop enables the outputs of a data buffer which then drives the peripheral device data signals on to the read data bus. The third flip flop output and the read enable signal are provided to a second AND gate which feeds back to the third flip flop to maintain its state until the read enable signal is de-asserted.