Christopher R Pasqualino

US Patent:

7092466, Aug 15, 2006

Filed:

May 13, 2002

Appl. No.:

10/144326

Inventors:

Sakyun Hwang - Fullerton CA, US
Seong-Ho Lee - Fullerton CA, US
Christopher R. Pasqualino - Glendora CA, US
Stephen G. Petilli - Pasadena CA, US
Hao O. Phung - Alhambra CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04L 7/00
H04L 25/00

US Classification:

375355, 375371

Abstract:

A deserializer that deserializes a high data rate bit stream to extract a set of bits contained therein includes a data sampler, a serial-to-parallel converter, a windowing block, and a phase error detection block. The data sampler over samples the high data rate bit stream to produce a serial group of samples corresponding to the set of bits of the high data rate bit stream. The serial-to-parallel converter couples to the data sampler and converts the serial group of samples into a parallel group of samples. The windowing block receives the parallel group of samples and produces output bits corresponding to the set of bits. The phase error detection block couples to the windowing block, detects errors in the alignment of the overlapping sampling windows of the windowing block, and directs the windowing block to adjust the operation. The phase error detection block and the windowing block compensate for bit stream jitter and intersymbol interference.

US Patent:

7099416, Aug 29, 2006

Filed:

Apr 30, 2002

Appl. No.:

10/135787

Inventors:

Christopher R. Pasqualino - Glendora CA, US
David V. Greig - Arcadia CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01B 1/10
H04B 3/00
H04L 7/00

US Classification:

375349, 375356, 375372, 375257

Abstract:

A receiver includes clock termination circuitry that is capable of applying either a terminating impedance or a high impedance to a transmission path that carries a clock signal. When multiple of these receivers are used to service data links that share a clock signal, one of the clock termination circuits applies the terminating impedance to the transmission path that carries the clock signal while the other clock termination circuit(s) applies a high impedance to the transmission path. The receiver also includes a plurality of high rate serial bit stream buffers and a clock signal buffer along with the clock termination circuitry. In other embodiments, the receiver includes a deserializer and may include a controller. The receiver may service a dual link Digital Visual Interface.

US Patent:

7120203, Oct 10, 2006

Filed:

May 14, 2002

Appl. No.:

10/145411

Inventors:

Jeffrey Bauch - Torrance CA, US
Richard Berard - Pasadena CA, US
Christopher R. Pasqualino - Glendora CA, US
Stephen G. Petilli - Pasadena CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04L 27/04

US Classification:

375295, 375256, 375257

Abstract:

A dual link transmitter constructed according to the present invention employs a single Phase Locked Loop (PLL) to service both a primary link and a secondary link during dual link mode operations. The structure of the dual link transmitter includes both a primary link PLL and a secondary link PLL. The primary link PLL produces a primary link clock and the secondary link PLL produces a secondary link clock. During dual single link operations, the primary link clock is used to service the primary link while the secondary link clock is used to service the secondary link. However, during dual link operations, the primary link clock is used to service both the primary link and the secondary link.

US Patent:

7250980, Jul 31, 2007

Filed:

Dec 27, 2001

Appl. No.:

10/034413

Inventors:

Christopher Pasqualino - Glendora CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04N 5/06
H04N 9/45
H04N 9/455

US Classification:

348521, 348194, 348525

Abstract:

The present invention relates to a system and method for generating a blanking period indicator signal from sync information in video timing. The invention comprises an auto polarity detect processor adapted to automatically detect the polarity of at least one sync signal and a generation processor adapted to generate a DE signal.

US Patent:

7254183, Aug 7, 2007

Filed:

Sep 5, 2006

Appl. No.:

11/516301

Inventors:

Jeffrey Bauch - Torrance CA, US
Richard Berard - Pasadena CA, US
Christopher R. Pasqualino - Glendora CA, US
Stephen G. Petilli - Pasadena CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04L 27/04

US Classification:

375295, 375256, 375257

Abstract:

A dual link transmitter constructed according to the present invention employs a single Phase Locked Loop (PLL) to service both a primary link and a secondary link during dual link mode operations. The structure of the dual link transmitter includes both a primary link PLL and a secondary link PLL. The primary link PLL produces a primary link clock and the secondary link PLL produces a secondary link clock. During dual single link operations, the primary link clock is used to service the primary link while the secondary link clock is used to service the secondary link. However, during dual link operations, the primary link clock is used to service both the primary link and the secondary link.

US Patent:

7308059, Dec 11, 2007

Filed:

Apr 24, 2002

Appl. No.:

10/131680

Inventors:

Christopher R. Pasqualino - Glendora CA, US
Po Ngan Zee - Glendale CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04L 7/00

US Classification:

375354

Abstract:

A dual link receiver terminates, recovers, channel aligns, and link aligns a plurality of primary link channels and a plurality of secondary link channels. The plurality of primary link channels and the plurality of secondary link channels are each received, bit recovered. synchronized, decoded and channel aligned. Then, the plurality of primary link channels and secondary link channels are link aligned. Link alignment operations first determine a relative misalignment between the plurality of primary link channels and the plurality of secondary link channels. A primary link delay is then applied to the primary link channels and a secondary link delay is then applied to the secondary link channels. A difference between the primary link delay and the secondary link delay is based upon the misalignment between the plurality of primary link channels and the plurality of secondary link channels. An enabling circuit precludes an incorrect blanking period indication.

US Patent:

7356051, Apr 8, 2008

Filed:

Sep 12, 2001

Appl. No.:

09/951671

Inventors:

Christopher Pasqualino - Glendora CA, US
Jeffrey S. Bauch - Torrence CA, US
Stephen Petilli - Pasadena CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04J 1/00

US Classification:

370490, 370509

Abstract:

One embodiment of the present invention uses an abbreviated blanking period, in comparison to the standard VESA and CEA-EIA blanking periods, in order to send data, including low bandwidth, non-timing information, over one or more channels of the digital video link. By shortening the blanking period, the amount of time available for sending data in each scan line is increased, enabling the system to send more data over each channel. The inactive video portion of a scan line sent during vertical sync may also be used to send additional digital data. Shortening the blanking periods and/or using the inactive video sections of the horizontal scan lines adds to the overall data capacity of the link and may be used to send other digital data, such as multi-channel audio, video, control, timing, closed captioning or other digital data.

US Patent:

7394406, Jul 1, 2008

Filed:

Jul 24, 2003

Appl. No.:

10/625974

Inventors:

Christopher R. Pasqualino - Glendora CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03M 7/00

US Classification:

341 50, 341 51

Abstract:

Encoding and decoding of video and non-video information may include creating a first symbol from a codeword. TERC4, TMDS and/or a guard band symbols may be generated from a portion or all of the first symbol during transmission. The TMDS symbol and/or the guard band symbol may be encoded so that they may be combined within a single symbol. At least a portion of the codeword may be TMDS encoded to generate a TMDS symbol for transmission. TMDS encoding of at least a portion of the first symbol may also generate a TERC4 symbol and/or a guard band symbol for the transmitted signal. The first symbol and the codeword may be generated from a portion or all of a received signal. The first codeword may be a 4-bit pre-TERC4 codeword, while the first symbol may be an 8-bit pre-TMDS symbol.