Christopher P Clark

US Patent:

6594802, Jul 15, 2003

Filed:

Nov 20, 2000

Appl. No.:

09/716583

Inventors:

Michael Ricchetti - Nashua NH
Christopher J. Clark - Durham NH
Bulent I. Dervisoglu - Mountain View CA

Assignee:

Intellitech Corporation - Durham NC

International Classification:

G06F 1750

US Classification:

716 4, 716 16, 714727

Abstract:

An access interface for accessing electrical nodes of an electronic circuit for programming, testing, and debugging the electronic circuit. The access interface includes a protocol generator and a data generator that may be programmed to apply control and/or data sequences directly to the electronic circuit. The access interface performs operational commands based upon a plurality of states included in a programmable state machine. By suitably programming the protocol generator, the data generator, and the state machine, electrical nodes of the electronic circuit can be accessed in reduced time using a reduced number of operations. The access interface is controlled by a test resource apparatus, which communicates with the electronic circuit connected to the access interface. The access interface may be implemented as a downloadable circuit, e. g. , it may be programmed into a programmable logic device by the test resource apparatus.

US Patent:

6957371, Oct 18, 2005

Filed:

May 10, 2002

Appl. No.:

10/142556

Inventors:

Michael Ricchetti - Nashua NH, US
Christopher J. Clark - Durham NH, US

Assignee:

Intellitech Corporation - Durham NH

International Classification:

G01R031/28

US Classification:

714733, 714724, 714735, 714726, 365201

Abstract:

An embedded electronic system built-in self-test controller architecture that facilitates testing and debugging of electronic circuits and in-system configuration of programmable devices. The system BIST controller architecture includes an embedded system BIST controller, an embedded memory circuit, an embedded IEEE 1149. 1 bus, and an external controller connector. The system BIST controller is coupled to the memory circuit and the IEEE 1149. 1 bus, and coupleable to an external test controller via the external controller connector. The external test controller can communicate over the IEEE 1149. 1 bus to program the memory and/or the system BIST controller circuitry, thereby enabling scan vectors to be debugged by the external test controller and then downloaded into the memory for subsequent application to a unit under test by the system BIST controller.

US Patent:

6988232, Jan 17, 2006

Filed:

Apr 9, 2002

Appl. No.:

10/119060

Inventors:

Michael Ricchetti - Nashua NH, US
Christopher J. Clark - Durham NH, US

Assignee:

Intellitech Corporation - Durham NH

International Classification:

G06F 11/00

US Classification:

714736

Abstract:

An architecture that provides stimulus data and verifies the response of multiple electronic circuits substantially in parallel for optimized testing, debugging, or programmable configuration of the circuits. The architecture includes a test bus, a primary test controller connected to the bus, and a plurality of local test controllers connected to the bus, in which each local test controller is coupleable to a respective circuit. The primary test controller sends stimulus data and expected response data over the bus to the respective local test controllers to perform parallel testing, debugging or programmable configuration of the circuits. Each local test controller applies the stimulus data and verifies the circuit response against the expected response data. Further, each local test controller stores the result of the verification for later retrieval by the primary test controller.

US Patent:

7093224, Aug 15, 2006

Filed:

Aug 28, 2001

Appl. No.:

09/941158

Inventors:

William R. Wheeler - Southborough MA, US
Matthew J. Adiletta - Worcester MA, US
Christopher Clark - Hopkinton MA, US
Timothy J. Fennel - Holliston MA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716 18

Abstract:

A technique for designing a logic circuit includes specifying a model. The model including combinatorial blocks, state elements and graphical library elements. The technique maintains a data structure representative of the model, and generates an architectural model and an implementation model from the data structure. The data structure represents a descriptive net list of the model. The architectural model includes C++ code and the implementation model includes Verilog.

US Patent:

7467342, Dec 16, 2008

Filed:

May 16, 2005

Appl. No.:

11/130332

Inventors:

Michael Ricchetti - Nashua NH, US
Christopher J. Clark - Durham NH, US

Assignee:

Intellitech Corporation - Durham NH

International Classification:

G01R 31/3187
G01R 31/40

US Classification:

714733, 714736

Abstract:

An embedded electronic system built-in self-test controller architecture that facilitates testing and debugging of electronic circuits and in-system configuration of programmable devices. The system BIST controller architecture includes an embedded system BIST controller, an embedded memory circuit, an embedded IEEE 1149. 1 bus, and an external controller connector. The system BIST controller is coupled to the memory circuit and the IEEE 1149. 1 bus, and coupleable to an external test controller via the external controller connector. The external test controller can communicate over the IEEE 1149. 1 bus to program the memory and/or the system BIST controller circuitry, thereby enabling scan vectors to be debugged by the external test controller and then downloaded into the memory for subsequent application to a unit under test by the system BIST controller.

US Patent:

7574637, Aug 11, 2009

Filed:

Nov 23, 2005

Appl. No.:

11/286915

Inventors:

Michael Ricchetti - Nashua NH, US
Christopher J. Clark - Durham NH, US

Assignee:

Intellitech Corporation - Durham NH

International Classification:

G01R 31/28
G11C 29/00

US Classification:

714724, 365201

Abstract:

A Parallel Test Architecture (PTA) is provided that facilitates concurrent test, debug or programmable configuration of multiple electronic circuits (i. e. , simultaneously). The PTA includes a communications path, a primary test controller, and a number of local test controllers. The primary controller provides stimulus, expected, and mask data to the local controllers over the communications path. The local controllers apply the stimulus data to the electronic circuits, receive resultant data generated by the circuits in response to the stimulus data, and locally verify the resultant data against the expected data substantially concurrently. When the communications path is implemented as an IEEE 1149. 1 (JTAG) test bus, the primary controller can provide the expected and mask data to the local controllers over the TDO and TRSTN lines while the TAP controllers of the electronic circuits are in the Shift-IR or Shift-DR state to enable concurrent testing over a traditional five wire multi-drop IEEE 1149. 1 test bus.

US Patent:

8325069, Dec 4, 2012

Filed:

Dec 22, 2009

Appl. No.:

12/645392

Inventors:

Vinodh Gopal - Westborough MA, US
Gilbert M. Wolrich - Framingham MA, US
Christopher F. Clark - Chandler AZ, US
Wadji K. Feghali - Boston MA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03M 7/34
H03M 7/38

US Classification:

341 51, 341 65, 341 67, 341 87

Abstract:

Systems, methods, and apparatus for a scalable processor architecture for variety of string processing application are described. In one such apparatus, n input first in, first out (FIFO) buffer stores an input stream. A plurality of memory banks store data from the input stream. A re-configurable controller processes the input stream. And an output FIFO buffer stores the processed input stream.

US Patent:

8484147, Jul 9, 2013

Filed:

Dec 19, 2008

Appl. No.:

12/340360

Inventors:

Christopher F. Clark - Berlin MA, US
Vinodh Gopal - Westborough MA, US
Gilbert M. Wolrich - Framingham MA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 17/00
G06N 5/02

US Classification:

706 46

Abstract:

A method and apparatus to perform pattern matching is provided. The apparatus includes a first storage to store data representing a first set of pattern components, and a second storage to store data representing a second set of pattern components each corresponding to one or more components of the first set of pattern components. A first pattern matcher is configured to detect in an input stream a first component of one or more patterns and to generate a signal indicative of the detection of the first component. A second pattern matcher is configured to receive the signal from the first pattern matcher and to detect if a second component of the one or more patterns of the set of patterns immediately follows the first component in the input stream.

Author:

Christopher Stuart Clark

ISBN #:

0192762141

Author:

Christopher Clark

ISBN #:

0194218309

Author:

Christopher Clark

ISBN #:

0194218317

Author:

Christopher Clark

ISBN #:

0194218325

Author:

Christopher Clark

ISBN #:

0194218333

Author:

Christopher Clark

ISBN #:

0194218341

Author:

Christopher Clark

ISBN #:

0194218511

Author:

Christopher Clark

ISBN #:

0198204566